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Apparatus for programming a programmable device, and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0232238 (2002-08-29)
발명자 / 주소
  • Anderson, Howard C.
  • Bersch, Danny Austin
  • Macbeth, Ian Craig
  • Schene, Christopher Robin
  • Streit, Timothy James
출원인 / 주소
  • Anadigm, Inc.
대리인 / 주소
    Wells St. John P.S.
인용정보 피인용 횟수 : 5  인용 특허 : 28

초록

An apparatus is provided for programming a programmable circuit device capable of realizing at least one sub-circuit by wiring together at least one circuit component. The programmable circuit device includes a programmable computing device, a user interface, and a design tool. The user interface is

대표청구항

1. An apparatus for programming a programmable device capable of realizing at least one sub-circuit by wiring together at least one circuit component, comprising:a programmable computing device; a design tool associated with the programmable computing device; and a self contained software agent havi

이 특허에 인용된 특허 (28)

  1. Stevens Kenneth S. ; Rotem Shai,ILX ; Ginosar Ran, Circuit synthesis and verification using relative timing.
  2. Yada Hideaki (Kawasaki JPX), Computer aided design support device.
  3. Hanrahan Shaila ; Phillips Christopher E., Configuration state memory for functional blocks on a reconfigurable chip.
  4. Bernard J. New, Dedicated function fabric for use in field programmable gate arrays.
  5. Kwiat Kevin Anthony, Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance.
  6. Baxter Michael A., Dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
  7. Roussakov Vladimir P.,RUX, Dynamically reconfigurable distributed integrated circuit processor and method.
  8. Martel Sylvain ; Lafontaine Serge R. ; Hunter Ian W., Dynamically reconfigurable hardware system for real-time control of processes.
  9. Alfke Peter H., FPGA control structure for self-reconfiguration.
  10. Burnham James L. ; Lawman Gary R. ; Linoff Joseph D., FPGA customizable to accept selected macros.
  11. Fallside Hamish T. ; Smith Michael J. S., FPGA-based communications access point and system for reconfiguration.
  12. Chatter Mukesh, High performance self modifying on-the-fly alterable logic FPGA, architecture and method.
  13. Levitt Marc E., Integrated circuit with identification signal writing circuitry distributed on multiple metal layers.
  14. Frink Craig R., Method and apparatus for controlling switching of connections among data processing devices.
  15. Anderson Howard C. ; Marcjan Cezary ; Anderson David J. ; Bersch Danny A., Method for configuring a programmable semiconductor device.
  16. Lawman Gary R. ; Linoff Joseph D. ; Wells Robert W., Method for configuring circuits over a data communications link.
  17. Carmichael Carl H. ; Theron Conrad A. ; St. Pierre ; Jr. Donald H., Method for reconfiguring a field programmable gate array from a host.
  18. Ellen Jean Stokes ; Ivan Matthew Milman, Method for securing sensitive data in a LDAP directory service utilizing a client and/or server control.
  19. Guccione Steven A., Method of designing FPGAs for dynamically reconfigurable computing.
  20. James L. Burnham ; Gary R. Lawman ; Joseph D. Linoff, Methods to securely configure an FPGA to accept selected macros.
  21. Pierzchala Edmund ; Perkowski Marek A., Programmable analog array circuit.
  22. Nishihara Yoshio,JPX, Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device.
  23. New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundarajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
  24. New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
  25. Ryan Arthur ; Andrade Hugo, Reconfigurable test system.
  26. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.
  27. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
  28. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.

이 특허를 인용한 특허 (5)

  1. Boger,Bentley; Brusko,Paul; Ramspeck,Alan, Adhesive system configuration tool.
  2. Hastings, Mark; Keeser, Chris, Graphical user interface for display of system resistance.
  3. Bhushan, Pranav; Chetput, Chandrashekar L.; O'Leary, Timothy Martin, Method and apparatus for AMS simulation of integrated circuit design.
  4. Bhushan, Pranav; Chetput, Chandrashekar L.; O'Leary, Timothy Martin, Method and apparatus for AMS simulation of integrated circuit design.
  5. Gupta, Amit, Processing a fast speed grade circuit design for use on a slower speed grade integrated circuit.
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