IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0445234
(2003-05-23)
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발명자
/ 주소 |
- Lien, Scott Te-Sheng
- Hubbard, John R.
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
10 인용 특허 :
9 |
초록
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An application specific processor for an application program is provided. First a software description, for example, a HDL description, of a processor is created. A user program is written using the processor's instruction set and compiled and/or assembled into object code. The software description
An application specific processor for an application program is provided. First a software description, for example, a HDL description, of a processor is created. A user program is written using the processor's instruction set and compiled and/or assembled into object code. The software description of the processor and the object code are combined and synthesized into a logic gate circuit description, which may be implemented in a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD) or any other Integrated Circuit (IC) having programmable logic modules. Typically, the logic gate circuit description is optimized, hence reducing the number of logic gates and the resources needed.
대표청구항
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1. A method for creating an application specific circuit design, the method comprising:processing computer language source code to produce object code;combining into a first software program, the object code and a second software program, the second software program describing a processor;associatin
1. A method for creating an application specific circuit design, the method comprising:processing computer language source code to produce object code;combining into a first software program, the object code and a second software program, the second software program describing a processor;associating the object code with a third software program describing a memory, and wherein the combining into the first software program, the object code and the second software program, comprises integrating the second software program and the third software program into the first software program; andconverting the first software program into a circuit description comprising a plurality of logic gates; andwherein said computer language source code is configured to execute a user application program using said processor's unmodified instruction set; andwherein the computer language source code comprises a plurality of instructions from an instruction set associated with the processor.2. The method of claim 1 wherein the converting comprises synthesizing and optimizing the first software program into the circuit description.3. The method of claim 1 wherein the processor is a general purpose microprocessor.4. The method of claim 1 wherein the first and second software programs comprise hardware description language statements.5. A method for processing source code by an integrated circuit having programmable logic modules, the method comprising:obtaining first code describing at least part of a processor, the processor having an associated set of instructions;generating the object code from the source code, the source code consisting of a plurality of commands from the associated set;generating second code describing a memory, the memory comprising the object code;combining the first and second code into third code, the third code describing at least part of the processor and at least part of the memory, the third code stored in a computer readable memory; andforming a netlist derived from the third code, the netlist for configuring the programmable logic modules to execute the object code.6. The method of claim 5 wherein the generating the object code from the source code comprises compiling or assembling, or a combination thereof, the source code to produce the object code.7. The method of claim 5 wherein the first and second code comprise hardware description language code.8. The method of claim 7 wherein the hardware description language code comprise VHDL or Verilog code.9. The method of claim 5 wherein the source code comprises assembly language code, the assembly language code related to the processor.10. The method of claim 5 wherein the source code comprises a high level language.11. The method of claim 10 wherein the high level language is selected from a group consisting of an assembly language, C, C++, C#, Java, NET., and VB/VBA.12. The method of claim 5 wherein the second code comprises an array describing the memory.13. The method of claim 5 wherein the netlist is an optimized netlist.14. The method of claim 5 further comprising:placing and routing the netlist; andconfiguring the programmable logic modules using the placed and routed netlist.15. The method of claim 5 wherein the forming a netlist derived from the third code comprises, synthesizing the netlist from the third code using a synthesis computer tool, the synthesis computer tool performing optimization operations in producing the netlist.16. A method for processing source code by an integrated circuit having programmable logic circuitry, the method comprising:obtaining first hardware description language (HDL) code for a processor;generating the object code from the source code;generating second hardware description language code describing a memory, the memory having the object code;wherein said object code excludes any change to an initial instruction set for said processor;integrating the first and second hardware description language code into third hardware description language code, the third hardware description language code describing the processor coupled to the memory;creating a netlist by synthesizing the third hardware description language code, wherein the synthesizing reduces the programmable logic circuitry needed to execute the object code;place and routing the netlist; andconfiguring the programmable logic circuitry using the placed and routed netlist.17. An application specific processor design, comprising:means for processing computer language source code to produce object code;said processing computer language source code comprising one of a plurality of user application programs configured to execute on a processor, wherein the computer language source code comprises a plurality of instructions from an instruction set associated with the processormeans for combining into a first software program, the object code and a second software program and a third software program, the second software program describing a processor and the third software program describing a memory; andmeans for converting the first software program into a circuit description comprising a plurality of logic gates.18. An application specific processor design, comprising:object code for an application program;a first hardware description language description of a processor configured to program an integrated circuit having programmable logic modules;wherein said object code is configured to execute on a predetermined initial set of processor operation codes for said processor;a second hardware description language description of a memory, the memory comprising the object code; anda synthesized netlist derived from the first hardware description language description and the second hardware description language description.19. The application specific processor design of claim 18, wherein synthesized netlist is used to program the integrated circuit having programmable logic modules.20. The application specific processor design of claim 18 further comprising a placed and routed netlist for programming the programmable logic modules, the placed and routed netlist derived from the synthesized netlist.21. The application specific processor design of claim 18 wherein the hardware description language is ABEL or VHDL or Verilog.
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