Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-003/356
H03K-003/00
출원번호
US-0876790
(2004-06-25)
발명자
/ 주소
Yin,Guangming
Fujimori,Ichiro
Hairapetian,Armond
출원인 / 주소
Broadcom Corporation
대리인 / 주소
Garlick Harrison &
인용정보
피인용 횟수 :
23인용 특허 :
119
초록▼
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like ar
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3 MOS logic with low power conventional CMOS logic. The combined C3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3 MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.
대표청구항▼
What is claimed is: 1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising: first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering
What is claimed is: 1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising: first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry is operable to process a first signal thereby generating a second signal; second circuitry coupled to the first circuitry and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuitry is operable to process the second signal thereby generating a third signal; wherein the first circuitry is coupled to a first power supply voltage; wherein the second circuitry is coupled to a second power supply voltage that is different than the first power supply voltage; and wherein the first power supply voltage is higher in magnitude than the second power supply. 2. The circuit of claim 1, further comprising: third first circuitry implemented using C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the third circuitry being configured to process the third signal thereby generating a fourth signal. 3. The circuit of claim 2, wherein: the third circuitry is coupled to the first power supply voltage. 4. The circuit of claim 2, wherein: the first signal has a first frequency; the second signal has a second frequency that is different than the first frequency; the third signal has the second frequency; and the fourth signal has the first frequency. 5. The circuit of claim 4, wherein: the second frequency is lower than the first frequency. 6. The circuit of claim 2, wherein: the first signal has a first frequency; the second signal includes a first plurality of signals, each signal of the first plurality of signals has a second frequency that is different than the first frequency; the third signal includes a second plurality of signals, each signal of the second plurality of signals has the second frequency; and the fourth signal has the first frequency. 7. The circuit of claim 6, wherein: the second frequency is lower than the first frequency. 8. The circuit of claim 2, wherein: the first signal has a first frequency; the first circuitry is a demultiplexer that is operable to deserialize the first signal thereby generating the second signal that includes a first plurality of signals, each signal of the first plurality of signals has a second frequency that is different than the first frequency; the second circuitry is an application specific integrated circuit (ASIC) that is operable to perform data monitoring and error correction when processing each signal of the first plurality of signals within the second signal thereby generating the third signal that includes a second plurality of signals, each signal of the second plurality of signals has the second frequency; the third circuitry is a multiplexer and clock multiplication unit (CMU) that is operable to serialize each signal of the second plurality of signals within the third signal thereby generating the fourth signal; and the fourth signal has the first frequency. 9. The circuit of claim 1, further comprising: a voltage generator that is operable to receive the first power supply voltage and to generate the second power supply voltage there from. 10. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising: first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry is operable to process a first signal thereby generating a second signal; second circuitry coupled to the first circuitry and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuitry is operable to process the second signal thereby generating a third signal; third circuitry implemented using C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the third circuitry being configured to process the third signal thereby generating a fourth signal; wherein the first circuitry is coupled to a first power supply voltage; wherein the second circuitry is coupled to the second power supply voltage that is different than the first power supply voltage; wherein the second power supply voltage is generated on-chip from the first power supply voltage; and wherein the third circuitry is coupled to the first power supply voltage. 11. The circuit of claim 10, further comprising: a voltage generator that is operable to receive the first power supply voltage and to generate the second power supply voltage there from. 12. The circuit of claim 10, wherein: the first signal has a first frequency; the second signal has a second frequency that is different than the first frequency; the third signal has the second frequency; and the fourth signal has the first frequency. 13. The circuit of claim 12, wherein: the second frequency is lower than the first frequency. 14. The circuit of claim 10, wherein: the first signal has a first frequency; the second signal includes a first plurality of signals, each signal of the first plurality of signals has a second frequency that is different than the first frequency; the third signal includes a second plurality of signals, each signal of the second plurality of signals has the second frequency; and the fourth signal has the first frequency. 15. The circuit of claim 14, wherein: the second frequency is lower than the first frequency. 16. The circuit of claim 10, wherein: the first signal has a first frequency; the first circuitry is a demultiplexer that is operable to deserialize the first signal thereby generating the second signal that includes a first plurality of signals, each signal of the first plurality of signals has a second frequency that is different than the first frequency; the second circuitry is an application specific integrated circuit (ASIC) that is operable to perform data monitoring and error correction when processing each signal of the first plurality of signals within the second signal thereby generating the third signal that includes a second plurality of signals, each signal of the second plurality of signals has the second frequency; the third circuitry is a multiplexer and clock multiplication unit (CMU) that is operable to serialize each signal of the second plurality of signals within the third signal thereby generating the fourth signal; and the fourth signal has the first frequency. 17. The circuit of claim 10, wherein: the first power supply voltage is higher in magnitude than the second power supply. 18. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising: a demultiplexer implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals; wherein the demultiplexer is operable to deserialize a first signal having a first frequency thereby generating a second signal that includes a first plurality of signals, each signal of the first plurality of signals has a second frequency that is different than the first frequency; an application specific integrated circuit (ASIC) coupled to the demultiplexer and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated; wherein the ASIC is operable to perform data monitoring and error correction when processing each signal of the first plurality of signals within the second signal thereby generating a third signal that includes a second plurality of signals, each signal of the second plurality of signals has the second frequency a multiplexer and clock multiplication unit (CMU) implemented using C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals; wherein the multiplexer and CMU is operable to serialize each signal of the second plurality of signals within the third signal thereby generating a fourth signal; wherein the demultiplexer is coupled to a first power supply voltage; wherein the ASIC is coupled to the second power supply voltage that is different than the first power supply voltage; and wherein the multiplexer and CMU is coupled to the first power supply voltage. 19. The circuit of claim 18, wherein: the second power supply voltage is generated on-chip from the first power supply voltage. 20. The circuit of claim 18, wherein: the first power supply voltage is higher in magnitude than the second power supply.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (119)
Ishii Naomitus (Yokohama JPX) Lamberton Marc (Antibes FRX) Molinengo Michel (Antibes FRX), Adaptation device and method for efficient interconnection of data processing devices and networks.
Ferraiolo Frank David ; Hoke Joseph Michael ; Patel Samir Kirit, Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources.
Canova ; Jr. Francis J. (Boynton Beach FL) Katz Neil A. (Parkland FL) Astarabadi Shaun (Irvine CA) Horton Robert L. (Alta Loma CA), Automatic device configuration for dockable portable computers.
Bantz David F. (Chappaqua NY) Cato Robert T. (Raleigh NC) Huang Chia-chi (Yorktown Heights NY), Broadcast-initiated bipartite frame multi-access protocol.
Robinson Mark T. (Carlsbad CA) Gardner Steven H. (San Diego CA) Wong Matt (San Diego CA) Kasmir Seton P. (San Diego CA) Balachandran Kumar (San Diego CA) Graham Sue (Encinitas CA) Schjelderup Gail (P, Cellular digtial packet data mobile data base station.
Mahany Ronald L. ; Meier Robert C. ; Luse Ronald E., Communication network having a plurality of bridging nodes which transmit a beacon to terminal nodes in power saving s.
Ronald L. Mahany ; Robert C. Meier ; Ronald E. Luse, Communication network having a plurality of bridging nodes which transmit a beacon to terminal nodes in power saving state that it has messages awaiting delivery.
Guay Bernard (Ottawa CAX) Altmann Michael (Kanata CAX), Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals.
Gastouniotis C. S. (Santa Barbara CA) Bandeira Nuno (Goleta CA) Gray Bruce E. (Murrysville PA) Seehoffer Scott H. (Uniontown PA), Duplex bi-directional multi-mode remote instrument reading and telemetry system.
Campo James A. (Brunswick OH) Sutherland Jeffrey W. (Tallmadge OH) Krill ; III Carl E. (Akron OH), Encoding and decoding system for electronic data communication system.
Moskowitz Jay (Hicksville NY) Karron Abraham (Long Beach NY) Squillante Peter (Central Islip NY) Kravitz Spencer (Hicksville NY), Handheld facsimile and alphanumeric message transceiver operating over telephone or wireless networks.
Gerowitz Robert Glen ; Gray Carl Thomas ; Marshall John ; Riedle Christopher G. ; Rizzo Raymond Paul, High speed parallel/serial link for data communication.
Hendrick Peter L. (Los Alamos NM) Speirs Donald F. (San Juan NM) Wolf Michael A. (Los Alamos NM), High speed system for reading and writing data from and into remote tags.
Fischer Michael A. (San Antonio TX) Cox William M. (San Antonio TX) McDougall Floyd H. (San Antonio TX), LAN with interoperative multiple operational capabilities.
Krebs Jay (Crystal Lake IL) Freeburg Thomas A. (Arlington Heights IL), Method and apparatus for communicating variable length messages between a primary station and remote stations of a data.
Stengel Robert E. (Ft. Lauderdale FL) Sharp Ronald E. (Plantation FL) Yester Francis R. (Arlington Heights IL), Method and apparatus for providing power conservation in a communication system.
Burke Christopher J. (Maple Valley WA) Chaffee Janice M. (Auburn WA) Nir Erez (Bellevue WA) Kee Thomas E. (Lynnwood WA), Method and apparatus for selecting between a plurality of communication paths.
Comroe Richard A. (Dundee IL) Grube Gary W. (Palatine IL), Method for inter operation of a cellular communication system and a trunking communication system.
Derby Jeffrey H. (Chapel Hill NC) Doeringer Willibald A. (Langnau CHX) Dykeman Harold D. (Rueschlikon NC CHX) Li Liang (Chapel Hill NC) Sandick Haldon J. (Durham NC) Vu Ken V. (Cary NC), Methods and apparatus for interconnecting local area networks with wide area backbone networks.
Koenck Steven E. ; Miller Phillip ; West Guy J. ; Mahany Ronald L. ; Kinney Patrick W., Modular portable data processing terminal having a higher layer and lower layer partitioned communication protocol stack for use in a radio frequency communications network.
Koenck Steven E. (Cedar Rapids IA) Miller Phillip (Cedar Rapids IA) West Guy J. (Cedar Rapids IA) Mahany Ronald L. (Cedar Rapids IA) Kinney Patrick W. (Cedar Rapids IA), Modular, portable data processing terminal for use in a radio frequency communication network.
Miller ; II Robert R. (Morris Township ; Morris County NJ) Partridge ; III B. Waring (Mendham NJ) Russell Jesse E. (Piscataway NJ) Schroeder Robert E. (Morris Township ; Morris County NJ), Multi-band wireless radiotelephone operative in a plurality of air interface of differing wireless communications system.
Pearson Gregory (Granada Hills CA) Melhorn Nathan R. (Framingham MA) Onarato Michael F. (Acton MA) Richards Craig A. (Wrentham MA), Multi-mode modem and data transmission method.
Gollnick Charles D. ; Luse Ronald E. ; Pavek John G. ; Sojka Marvin L. ; Cnossen James D. ; Danielson Arvin D. ; Mahany Ronald L. ; Detweiler Mary L. ; Spiess Gary N. ; West Guy J. ; Young Amos D. ; , Network supporting roaming, sleeping terminals.
Mitchell Dennis R. (San Jose CA) Molenda James R. (Fremont CA) Nakamura Karl S. (Palo Alto CA), Portable computer with removable and replaceable add-on modules.
Zook Ronald E. (Boulder CO) Gombrich Peter P. (Boulder CO), Portable handheld terminal including optical bar code reader and electromagnetic transceiver means for interactive wirel.
Bertagna Richard A. (San Dimas CA) Berry Dickey J. (LaVerne CA), Portable transaction monitoring unit for transaction monitoring and security control systems.
Meyerson Robert F. (Captiva Island FL) Chang Yung-Fu (Medina OH) Wang Ynjiun P. (Ft. Myers FL) Wall Daniel G. (Union Town OH), Portable work slate computer with multiple docking positions for interchangeably receiving removable modules.
Olnowich Howard T. (Endwell NY), Protocol-to-protocol translator for interfacing disparate serial network nodes to a common parallel switching network.
Wilson Alan L. (Hoffman Estates IL) Muri David L. (Sunrise FL) Branch Tony R. (Sunrise FL), Reduction of power consumption in a portable communication unit.
Gilbert Sheldon L. (San Diego CA) Heide Carolyn L. (Lincolnshire IL) Director Dennis L. (Wilmette IL), Reservation-based polling protocol for a wireless data communications network.
Richter Roger K. (Round Rock TX) Sharp Robert O. (Round Rock TX) Stephenson Quentin H. (Austin TX), System for enabling first computer to communicate over switched network with second computer located within LAN by using.
Danielson Arvin D. (Cedar Rapids IA) Kubler Joseph J. (Nederland CO) Durbin Dennis A. (Cedar Rapids IA) Morris Michael D. (Cedar Rapids IA) Cargin ; Jr. Keith K. (Cedar Rapids IA), System including multiple device communications controller which coverts data received from two different customer trans.
Dowdell Ed (Massapequa NY) Giacopelli Dan (Deer Park NY) Taylor Alvin (Bayside NY) Nathanson Rex (Dix Hills NY) Dzurney Ray (Kings Park NY), Wireless communication system.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.