IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0991412
(2001-11-16)
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발명자
/ 주소 |
- Herron,Nigel G.
- Thorne,Eric J.
- Wang,Qingqi
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
16 인용 특허 :
83 |
초록
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A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing
A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.
대표청구항
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What is claimed is: 1. A method for testing a fixed logic device formed within a gasket, comprising: receiving an FPGA scan chain and configuring an FPGA fabric portion for a specified test; producing a first test signal and a second test signal in the FPGA fabric portion; providing the first test
What is claimed is: 1. A method for testing a fixed logic device formed within a gasket, comprising: receiving an FPGA scan chain and configuring an FPGA fabric portion for a specified test; producing a first test signal and a second test signal in the FPGA fabric portion; providing the first test signal as input to an isolation circuit element; providing the second test signal to a programmable interconnect resource; selecting for input to the fixed logic device between the first signal and the second signal in response to a test mode configured in the FPGA fabric portion; receiving an output test signal from the fixed logic device; applying a signature function to the received output test signal; repeating the producing, receiving and applying steps for a specified number of times; and determining if a value of the signature function corresponds to an expected value. 2. The method of claim 1 further comprising the step of isolating the fixed logic device that is to be tested. 3. The method of claim 1 further comprising the step of receiving an output test signal from the fixed logic device by way of an isolation circuit element. 4. The method of claim 1 wherein the determining step is performed by logic within an FPGA fabric portion. 5. The method of claim 1 wherein the determining step is performed by an external tester. 6. The method of claim 1 wherein the determining step includes the step of comparing the signature to an expected value. 7. An FPGA, comprising: an FPGA fabric portion; a Gasket formed at least partially within the FPGA fabric portion, the Gasket forming interfacing logic between an embedded core device and the fabric portion; and isolation circuitry formed within the Gasket, the isolation circuitry being serially coupled to receive test signals from the FPGA fabric portion, isolate the embedded core device from the Gasket during testing of the embedded core device, and isolate the Gasket from the embedded core device during testing of the Gasket. 8. The FPGA of claim 7 wherein the isolation circuitry includes a multiplexer array, which multiplexer array facilitates sending test signals directly to the embedded core device. 9. The FPGA of claim 7 wherein the isolation circuitry includes a multiplexer array, which multiplexer array facilitates sending test signal outputs directly from the embedded core device to the FPGA fabric. 10. An FPGA, comprising: an FPGA fabric portion; a Gasket formed at least partially within the FPGA fabric portion, the Gasket forming interfacing logic between an embedded core device and the fabric portion; a first multiplexer coupled to receive a first test signal from the FPGA fabric portion by way of a communication path formed within the Gasket portion, wherein the communication path is accessible while the FPGA is configured for testing at least a portion of the Gasket; and a fixed logic device formed within the Gasket, the fixed logic device being coupled receive a second test signal from the FPGA fabric portion and provide the second test signal to the first multiplexer, wherein the first multiplexer selects between the first test signal received from the FPGA fabric portion and the second test signal for input to the embedded core device in response to a test mode configuration of the FPGA fabric portion. 11. The FPGA of claim 10, further comprising a second multiplexer coupled to receive an output signal from an embedded core device and a third test signal from the FPGA fabric portion, and to select between the third test signal and the output signal from the embedded core device for input to the fixed logic device in response to a test mode configuration of the FPGA fabric portion. 12. An FPGA, comprising: ID circuitry for delivering a device ID to an embedded device; input circuitry for receiving test signals from test circuitry; and multiplexer circuitry coupled to receive input test signals and control signals from the input circuitry and ID information from the ID circuitry, and to produce selected input signals to the embedded device. 13. The FPGA of claim 12 further comprising test circuitry coupled to the input circuitry to produce test and control signals thereto. 14. The FPGA of claim 12 being configurable to connect the input circuitry to pins that may be connected to external test equipment, which external test equipment is for producing test signals that are received by the multiplexer circuitry and conducted to the inputs of the embedded device. 15. An FPGA configured in a test mode of operation, comprising: an FPGA fabric portion; a Gasket formed at least partially within the FPGA fabric portion, the Gasket forming interfacing logic between an embedded core device and a subset of the FPGA fabric portion; a first multiplexer coupled to receive a first test signal from the FPGA fabric portion by way of a communication path formed within the Gasket portion, wherein the communication path is accessible while the FPGA is configured for testing at least a portion of the Gasket; a fixed logic device formed within the Gasket, the fixed logic device being coupled to receive a second test signal from the FPGA fabric portion and provide the second test signal to the first multiplexer, wherein the first multiplexer selects between the first test signal received from the FPGA fabric portion and the second test signal for input to the embedded core device in response to a test mode configuration of the FPGA fabric portion; first logic circuitry forming a plurality of latches for receiving an FPGA scan chain containing test vectors; second logic circuitry forming a test output signature generator; third logic circuitry configured for performing a specified test; and fourth logic circuitry for determining whether the FPGA passed or failed a test. 16. The FPGA of claim 15 wherein each of the first, second and third logic circuitry are formed to communication with the fixed logic device. 17. The FPGA of claim 16 wherein the fixed logic device is an embedded core processor. 18. A programmable logic device (PLD), comprising: an integrated circuit, including, a configuration memory arranged for storage of bit values that program functions of programmable logic resources and programmable interconnect resources of the PLD; a plurality of programmable logic resources coupled to the configuration memory; a plurality of programmable interconnect resources coupled to the configuration memory and to the programmable logic resources; a fixed logic circuit; and an interface circuit including, a plurality of programmable switches coupled to the subset of the programmable interconnect resources; a fixed interface circuit coupled to the plurality of switches; and a selector circuit arrangement coupled to the fixed interface circuit, to the fixed logic circuit, and to the interconnect resources, the selector circuit arrangement adapted to, for input to each of a plurality of input pins of the fixed logic circuit, select between a signal from the fixed interface and a signal from the interconnect resources. 19. The PLD of claim 18, wherein the selector circuit is further adapted to, for input to each of a plurality of input ports of the fixed interface circuit, select between a signal from an output port of the fixed logic circuit and a signal received from the interconnect resources. 20. The PLD of claim 19, wherein: the integrated circuit further includes a non-volatile memory adapted for storage of a device identifier; and the interface circuit further includes an ID selector circuit arrangement coupled to the fixed logic circuit, to the interconnect resources, and to the non-volatile memory, the ID selector circuit arrangement adapted to, for input to each of at least two input ports of the fixed logic circuit, select between a signal received from the interconnect resources and a signal received from the non-volatile memory. 21. The PLD of claim 19, wherein the fixed logic core is a microprocessor.
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