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A solid state thermal control device contains a substrate and a plurality of solid state thermal elements on the substrate. The thermal elements are adapted to provide thermal control to a device under test (DUT). Each solid state thermal element contains at least one solid state heater and an activ

A solid state thermal control device contains a substrate and a plurality of solid state thermal elements on the substrate. The thermal elements are adapted to provide thermal control to a device under test (DUT). Each solid state thermal element contains at least one solid state heater and an active control circuit adapted to control a thermal output of the heater. Optionally, the each thermal element may also include a solid state temperature sensor.

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What is claimed is: 1. A solid state thermal control device, comprising: a substrate; and a plurality of substantially thermally isolated solid state thermal elements on the substrate adapted to provide thermal control to a device under test (DUT); wherein each solid state thermal element comprises

What is claimed is: 1. A solid state thermal control device, comprising: a substrate; and a plurality of substantially thermally isolated solid state thermal elements on the substrate adapted to provide thermal control to a device under test (DUT); wherein each solid state thermal element comprises: (a) at least one solid state heater; and (b) a control logic circuit adapted to control a thermal output of the solid state heater. 2. The device of claim 1, wherein: the substrate comprises a semiconductor wafer; the thermal elements are arranged in or over the semiconductor wafer such that one or more thermal elements are adapted to provide thermal control to each die of a wafer under test; and the control circuit comprises an active semiconductor logic control circuit. 3. The device of claim 2, wherein the heaters comprise integrated circuit resistors. 4. The device of claim 2, wherein the heaters comprise solid state thermoelectric or thermionic devices. 5. The device of claim 2, wherein the heaters comprise microelectromechanical heat pumps. 6. The device of claim 2, further comprising at least 1000 thermal elements on the substrate. 7. The device of claim 2, wherein a first active control circuit is adapted to actively control a magnitude of the thermal output of a first heater located in a same first thermal element as the first active control circuit. 8. The device of claim 7, wherein the plurality of thermal elements are adapted to provide different thermal outputs to maintain the DUT with a non-uniform spatial power dissipation during electrical testing or bum-in processing at a substantially uniform temperature during the electrical testing or bum-in processing. 9. The device of claim 7, wherein the thermal control device is adapted to provide thermal control for different types of DUTs undergoing electrical testing or bum-in processing independent of spatial or temporal variation in DUT power dissipation during the testing. 10. The device of claim 7, wherein the first active control circuit is adapted to actively control a magnitude of the thermal output of the first heater and of a second heater which are located in the first thermal element. 11. The device of claim 2, further comprising a solid state temperature sensor located in the plurality of thermal elements. 12. The device of claim 11, further comprising a plurality of thermal isolation regions which substantially thermally isolate adjacent thermal elements, wherein the isolation regions comprise at least one of air gap isolation trenches, trenches filled with low thermal conductivity material or semiconductor regions of lower thermal conductivity than the thermal elements. 13. The device of claim 11, wherein the plurality of thermal elements are adapted to be set to a single predetermined temperature. 14. The device of claim 1, wherein: the substrate comprises a portion of a semiconductor wafer, and the thermal elements are arranged in or over the portion of the semiconductor wafer such that two or more thermal elements are adapted to provide thermal control to a device under test which comprises a packaged semiconductor device, an unpackaged semiconductor die or a portion of a wafer under test. 15. The device of claim 11, wherein the active control circuits are adapted to continuously adjust the thermal output of the heaters based on temperature measured by the plurality of temperature sensors. 16. The device of claim 1, wherein the control circuits are adapted to adjust the thermal output of the heaters based on temperature measured by a plurality of second temperature sensors located on the DUT. 17. The device of claim 1, wherein the control circuits are adapted to adjust the thermal output of the heaters based on determined DUT power dissipation. 18. The device of claim 1, wherein the active control circuits are adapted to adjust the thermal output of the heaters based on a stored profile of DUT power dissipation. 19. A semiconductor wafer testing system, comprising: (a) thermal control wafer, comprising: a semiconductor wafer substrate; a plurality of solid state thermal elements on the substrate adapted to provide thermal control to a wafer under test (WUT), wherein each thermal element comprises at least one solid state heater and a control logic circuit adapted to control a thermal output of the solid state heater; (b) an electrical testing or bum-in processing probe located opposite a first side of the thermal control wafer, such that a wafer under test (WUT) location opening is created between the thermal control wafer and the probe; and (c) a thermal reservoir located in thermal contact with a second side of the thermal control wafer. 20. The system of claim 19, wherein: the thermal elements are arranged in or over the substrate such that one or more thermal elements are adapted to provide thermal control to one die of the WUT; and the control logic circuits comprise active semiconductor logic control circuits located in or over the substrate. 21. The system of claim 20, wherein the heaters comprise at least one of integrated circuit resistors, solid state thermoelectric or thermionic devices and microelectromechanical heat pump devices. 22. The system of claim 21, further comprising at least 1000 thermal elements on the substrate. 23. The system of claim 20, wherein each active control circuit is adapted to independently control a magnitude of the thermal output of a heater in a same thermal element, such that the plurality of thermal elements provide a different amount of thermal output to maintain the WUT with a non-uniform spatial power dissipation during electrical testing or bum-in processing at a substantially uniform temperature during the electrical testing or bum-in processing. 24. The system of claim 23, wherein the system is adapted to provide thermal control for different types of WUTs undergoing electrical testing or bum-in processing independent of spatial or temporal variation in WUT power dissipation during the testing. 25. The system of claim 19, further comprising a plurality of solid state temperature sensors located in the plurality of thermal elements. 26. The system of claim 25, further comprising a plurality of thermal isolation regions which substantially thermally isolate adjacent thermal elements. 27. The system of claim 26, wherein a thermal resistance between adjacent thermal elements is at least two times larger than a thermal resistance between the thermal reservoir and a first thermal element, and at least two times larger than a thermal resistance between the first thermal element and a WUT located in the WUT location opening. 28. The system of claim 25, where the control circuits are adapted to actively adjust the thermal output of the heaters based on temperature measured by the temperature sensors. 29. The system of claim 28, wherein the control logic circuits are adapted to convert the measured temperature to a first signal whose frequency is a function of the measured temperature. 30. The system of claim 19, where the control logic circuits are adapted to adjust the thermal output of the heaters based on one of: i) a temperature measured by a plurality of temperature sensors located on the WUT; ii) a determined WUT power dissipation; or iii) a stored profile of WUT power dissipation. 31. The system of claim 28, wherein the control logic circuits are adapted to extrapolate WUT die temperature from the first signal and to adjust the thermal output of the heaters based on comparing the extrapolated WUT die temperature to a set point temperature. 32. The system of claim 31, further comprising: a housing in which the thermal reservoir which comprises a thermal chuck, the thermal control wafer and the testing probe are located; and a central controller located remote from the thermal control wafer, which is adapted to control the control logic circuits located on the thermal control wafer. 33. A method of testing a DUT, comprising: placing a first side of a DUT in thermal contact with a thermal control substrate containing a plurality of solid state thermal elements; placing an electrical testing probe in contact with a second surface of the DUT; performing electrical testing or bum-in processing of the DUT, wherein the DUT in an unheated state has at least one of a non-uniform spatial and temporal temperature or power dissipation during the testing; and heating the DUT using the solid state thermal elements such that the DUT has a substantially uniform respective spatial, temporal or spatial and temporal temperature profile during testing. 34. The method of claim 33, wherein: the thermal control substrate contacts a thermal reservoir; the thermal control substrate comprises a semiconductor wafer containing at least 1000 thermal elements in or above its surface; the thermal elements comprise at least one solid state heater and an control circuit; the DUT comprises a semiconductor wafer under test (WUT); at least one thermal element is located in thermal contact with a first region on the WUT; and the at least one thermal element provides a substantially uniform spatial or temporal temperature profile for the first region. 35. The method of claim 33, wherein the thermal elements provide a substantially uniform spatial temperature profile across the WUT having a non-uniform spatial temperature or power dissipation during electrical testing or bum-in processing. 36. The method of claim 33, wherein the thermal elements provide a substantially uniform temporal temperature profile across an active area of the WUT having a non-uniform temporal temperature or power dissipation during electrical testing or bum-in processing. 37. The method of claim 33, wherein the thermal elements provide a substantially uniform spatial and temporal temperature profile across an active area of the WUT having a non-uniform spatial and temporal temperature or power dissipation during electrical testing or bum-in processing. 38. The method of claim 34, further comprising: individually measuring a temperature of thermal elements using temperature sensors located in the thermal elements; providing measured temperature data to active logic circuits located in the thermal elements; extrapolating individual WUT region temperature from the measured temperature of the thermal elements; determining if the extrapolated temperature of at least one WUT region deviates from a set point temperature by more than a first amount; and independently controlling the magnitude of the thermal output of the plurality of the solid state heaters located in the thermal elements. 39. The method of claim 38, wherein the measured temperature is continuously provided to a plurality of logic circuits located on the thermal control substrate, which continuously individually control the magnitude of the thermal output of one or more heaters located in a same thermal element as a given logic circuit. 40. The method of claim 39, wherein the measured temperature is converted to a first signal whose frequency is a function of the measured temperature. 41. The method of claim 33, wherein: the thermal control substrate comprises a portion of a semiconductor wafer; the DUT comprises a portion of a semiconductor wafer under test, a packaged semiconductor device or an unpackaged semiconductor die; and at least two thermal elements are located in thermal contact with the DUT and provide a substantially uniform spatial or temporal profile for the DUT. 42. The method of claim 33, further comprising changing a set point temperature of the thermal elements without handling, disturbing, or recontacting the DUT. 43. The method of claim 33, further comprising measuring DUT temperature using a plurality of temperature sensors located on the DUT and adjusting the heating of the DUT by the thermal elements based on the measured temperature. 44. The method of claim 33, further comprising determining DUT power dissipation and adjusting the heating of the DUT by the thermal elements based on the determined power dissipation. 45. The method of claim 33, further comprising storing a DUT power dissipation profile and adjusting the heating of the DUT by the thermal elements based on the stored power dissipation profile. 46. The method of claim 34, wherein: the thermal reservoir comprises a thermal chuck; the electrical testing probe comprises a wafer with pads which contact microspring contactors located on the WUT; and performing electrical testing or bum-in processing comprises simultaneously performing electrical testing or bum-in processing of a plurality of die of the WUT.