IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0293259
(2002-11-14)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Sterne, Kessler, Goldstein &
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인용정보 |
피인용 횟수 :
2 인용 특허 :
12 |
초록
▼
A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delaye
A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current. The logic device output port is configured to output an output signal responsive to the delayed signal and the corresponding current.
대표청구항
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What is claimed is: 1. A circuit comprising: a first stage including first and second active devices, each including three nodes, a junction formed of first nodes of the first and second devices forming a first circuit input port configured to receive an input signal, a junction formed of respectiv
What is claimed is: 1. A circuit comprising: a first stage including first and second active devices, each including three nodes, a junction formed of first nodes of the first and second devices forming a first circuit input port configured to receive an input signal, a junction formed of respective second and third nodes of the first and second devices forming a first stage output port configured to output a delayed signal; a second stage including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a first second stage input port, the first second stage input port being coupled to the first stage output port and (ii) an output port formed of a junction of a respective one of second and third nodes of the third and sixth active devices and the other of the second and third node of the fourth active device, the output port being configured to output an output drive signal; and a charge storing device configured to sense a rate of change of predetermined characteristics of the input signal, the charge storing device having a first end forming a second circuit input port and a second end coupled to a first node of the fifth and sixth devices, the other of the second and third node of the fifth device being coupled to an open node of the fourth device; wherein the second circuit input port is configured to receive the input signal; and wherein the first output drive signal is responsive to the delayed signal and the sensed rate of change. 2. The circuit of claim 1, wherein the first stage includes an inverter. 3. The circuit of claim 2, wherein the inverter includes a number of active devices. 4. The circuit of claim 3, wherein the active device includes transistors. 5. The circuit of claim 4, wherein the transistors include p-channel metal oxide semiconductor devices and n-channel metal oxide semiconductor devices. 6. The circuit of claim 5, wherein the first nodes are gates, the second nodes are sources, and the third nodes are drains. 7. The circuit of claim 6, wherein the charge storing device is a capacitor. 8. The circuit of claim 7, wherein the second stage includes at least one of a NAND gate and a NOR gate. 9. The circuit of claim 1, wherein the predetermined characteristics include voltage. 10. The circuit of claim 1, further comprising an impedance device coupled to the first end of the charge storing device. 11. A circuit comprising: a first portion including: a first inverter including first and second active devices, each including first, second, and third nodes, a junction formed of the first nodes of the first and second devices forming a first inverter input port configured to receive a first input signal, a junction formed of the respective second and third nodes of the first and second devices forming a first inverter output port configured to output a first delayed signal; a NAND gate including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a NAN) gate input port, the NAND gate input port being coupled to the first inverter output port and (ii) a NAND gate output port formed of a junction of second nodes of the third and sixth active devices and a third node of the fourth active device, the NAND gate output port being configured to output a first output drive signal; and a first charge storing device configured to sense a rate of change of predetermined characteristics of the first input signal, the charge storing device having a first end forming a second first portion input port and a second end coupled to a first node of the fifth and sixth devices, a third node of the fifth device being coupled to a second node of the fourth device; wherein the first portion input port is configured to receive the first input signal; and wherein the first output drive signal is responsive to the first delayed signal and the sensed rate of change of the first input signal; and a second portion including: a second inverter including first and second active devices, each including first, second, and third nodes, a junction formed of the first nodes of the first and second devices forming a second inverter input port configured to receive a second input signal, a junction formed of the respective second and third nodes of the first and second devices forming a second inverter output port configured to output a second delayed signal; a NOR gate including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a NOR gate input port, the NOR gate input port being coupled to the second inverter output port and (ii) a NOR gate output port formed of a junction of third nodes of the third and sixth active devices and a second node of the fourth active device, the NOR gate output port being configured to output a second output drive signal; and a second charge storing device configured to sense a rate of change of predetermined characteristics of the second input signal, the second charge storing device having a first end forming a second portion input port and a second end coupled to a first node of the fifth and sixth devices, a second node of the fifth device being coupled to a third node of the fourth device; wherein the second portion input port is configured to receive the second input signal; and wherein the second output drive signal is responsive to the second delayed signal and the sensed rate of change of the second input signal. 12. The circuit of claim 11, wherein the active devices include transistors. 13. The circuit of claim 12, wherein the first nodes are gates, the second nodes are sources, and the third nodes are drains. 14. The circuit of claim 13, wherein the first and second charge storing devices are capacitors. 15. The circuit of claim 14, wherein the predetermined characteristics include voltage. 16. The circuit of claim 15, further comprising first and second impedance devices having respective first ends respectively coupled to the first ends of the first and second charge storing devices.
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