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A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameter values. The data processor is

A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameter values. The data processor is operated based on a processing clock having a frequency that is (e.g., ten or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. The receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

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What is claimed is: 1. A receiver unit, comprising: a first buffer operative to receive and store digitized samples comprising multiple instances of a received signal; a data processor coupled to the first buffer and operative to (a) retrieve different segments of the digitized samples one segment

What is claimed is: 1. A receiver unit, comprising: a first buffer operative to receive and store digitized samples comprising multiple instances of a received signal; a data processor coupled to the first buffer and operative to (a) retrieve different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances, (b) process two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples, (c) decover the despread samples with a channelization code of programmable length to provide decovered symbols, (d) demodulate the decovered symbols to provide demodulated symbols, and (e) combine the demodulated symbols from the multiple signal instances to provide processed symbols; a controller being operative to direct the data processor; a microcontroller coupled to the data processor and the controller, the microcontroller being operative to receive tasks from the controller, instantiate a state machine for each task, and direct the data processor to process the retrieved different segments; and an address generator coupled to the first buffer and the controller, the address generator being operative to implement a counter to control a write address for writing digitized samples to the first buffer, the counter being operative to send a signal to the controller to initiate processing of the stored samples by the data processor. 2. The receiver unit of claim 1, wherein the controller is operative to dispatch tasks for the data processor and to process signaling data from the data processor. 3. The receiver unit of claim 1, wherein the micro-controller is operative to receive the tasks and generate a set of control signals to direct the operation of the first buffer and the data processor to execute the dispatched tasks. 4. The receiver unit of claim 1, wherein the clock a frequency of the data processor is at least ten times higher than the sample rate. 5. The receiver unit of claim 1, wherein the receiver unit is configured for operation in a high data rate (HDR) CDMA system. 6. The receiver unit of claim 1, wherein the controller has a time tracking loop operative to track movement of one of the multiple signal instances being processed by the data processor, and further being configured to generate a time offset used to retrieve a segment of the digitized samples in the first buffer containing said one of the multiple signal instances in response to the time tracking loop. 7. The receiver unit of claim 1 wherein the data processor is further configured to coherently combine the correlated samples from said two or more of the segments to generate processed symbols. 8. A receiver unit, comprising: a first buffer operative to receive and store digitized samples at a particular sample rate; and a data processor coupled to the first buffer and operative to retrieve segments of the digitized samples from the first buffer and to process the retrieved segments with a particular set of parameter values, wherein the data processor is operated based on a processing clock having a frequency that is higher than the sample rate, and wherein the data processor includes a correlator operative to despread the retrieved segments of the digitized samples with corresponding segments of PN (pseudo-random noise) despreading sequences to provide correlated samples, the correlator including an interpolator operative to receive and interpolate the despread samples to generate interpolated samples that are provided as the correlated samples, and wherein the interpolator includes one or more pairs of scaling elements, each of the scaling elements operative to receive and scale respective despread samples with a particular gain to generate scaled samples, and one or more summer, each of the summers coupled to a respective pair of scaling elements and operative to receive and sum the scaled samples from the pair of scaling elements to generate the interpolated samples. 9. A receiver unit, in a wireless communications system, comprising: a first buffer operative to receive and store digitized samples at a particular sample rate; a data processor coupled to the first buffer and operative to retrieve segments of the digitized samples from the first buffer and to process each of the retrieved segments with a particular set of parameter values, wherein the data processor is operated based on a processing clock having a frequency that is higher than the sample rate; a controller coupled to the data processor and operative to dispatch tasks for the data processor and to process signaling data from the data processor; and a micro-controller coupled to the controller and operative to receive the dispatched tasks and to generate a set of control signals to direct the operation of the first buffer and the data processor to execute the dispatched tasks, wherein the micro-controller includes a set of latches operative to latch a dispatched task and one or more parameter values to be applied for the dispatched task, at least one counter, each of the counters coupled to a respective latch and operative to provide an indicator signal based on a value stored in the latch, and a sequencing controller operative to receive at least one indicator signal and the dispatched task and to generate the set of control signals. 10. The receiver unit of claim 9, wherein the controller is operative to perform pilot processing and time tracking for each of the signal instances being processed. 11. The receiver unit of claim 9, wherein the controller is operative to perform lock detection for each of the signal instances being processed. 12. The receiver unit of claim 9, wherein the controller is operative to perform frequency tracking of the digitized samples. 13. The receiver unit of claim 9, further comprising: a receiver operative to receive the multiple instances of the signal to provide the digitized samples. 14. The receiver unit of claim 9, wherein the data processor includes a correlator operative to despread the retrieved segments of digitized samples with corresponding segments of PN (pseudo-random noise) despreading sequences to provide correlated samples. 15. The receiver unit of claim 14, wherein the data processor further includes a symbol demodulator and combiner coupled to the correlator and operative to receive and process the correlated samples to provide processed symbols. 16. The receiver unit of claim 15, wherein the symbol demodulator and combiner includes a decover element operative to receive and decover the correlated samples with one or more channelization codes to provide decovered symbols. 17. The receiver unit of claim 16, wherein the channelization codes are Walsh codes each having a length that is programmable and defined by one of the sets of the parameter values. 18. The receiver unit of claim 16, wherein the decover element is implemented with a fast Hadamard transform (FHT) element having L stages. 19. The receiver unit of claim 18, wherein the FHT element is operative to receive and process inphase and quadrature correlated samples on alternating clock cycles. 20. The receiver unit of claim 18, wherein the FHT element is operative to perform decovering with one or more Walsh symbols of a length of 1, 2, 4, 8, 16, 32, 64, or 128. 21. The receiver unit of claim 16, wherein the symbol demodulation and combiner further includes a pilot demodulator coupled to the decover element and operative to demodulate the decovered symbols with pilot symbols to provide demodulated symbols. 22. The receiver unit of claim 21, wherein the symbol demodulator and combiner further includes a symbol accumulator coupled to the pilot demodulator and operative to accumulate the demodulated symbols from multiple signal instances to provide the processed symbols. 23. The receiver unit of claim 14, wherein the data processor further includes an accumulator coupled to the correlator and operative to receive and process the correlated samples to provide accumulated results. 24. The receiver unit of claim 23, wherein the accumulator includes a plurality of accumulate elements, each accumulate element operative to provide pilot signal estimate for said different time offsets a particular time offset. 25. The receiver unit of claim 23, wherein the accumulator is operative to accumulate the correlated samples over a programmable time interval to provide pilot signal estimates. 26. The receiver unit of claim 15, wherein the data processor further includes a second buffer coupled to the symbol demodulation and combiner and operative to store the processed symbols. 27. The receiver unit of claim 26, wherein the second buffer is operative to provide the processed symbols to a subsequent signal processing element in an output order that is different from an input order to provide de-interleaving of the processed symbols. 28. The receiver unit of claim 27, wherein the second buffer includes at least two sections, one section operative to store processed symbols for a current packet being processed and another section operative to store processed symbols for a prior processed packet to be provided to the subsequent signal processing element. 29. The receiver unit of claim 14, wherein the correlator includes a set of K multipliers operative to concurrently despread sets of up to K complex digitized samples. 30. The receiver unit of claim 29, wherein the correlator further includes a set of K summers coupled to the set of K multipliers, each summer operative to receive and sum pairs of samples from two of the multipliers. 31. The receiver unit of claim 14, wherein the correlator includes an interpolator operative to receive and interpolate the despread samples to generate interpolated samples that are provided as the correlated samples. 32. The receiver unit of claim 9, wherein the controller is operative to instantiate a timing state machine for each signal instance being processed. 33. The receiver unit of claim 32, wherein each instantiated timing state machine includes a time tracking loop operative to track movement of the signal instance being processed. 34. The receiver unit of claim 9, wherein the controller is operative to receive a timing signal and initiate processing of the segments of digitized samples in response to the received timing signal. 35. The receiver unit of claim 34, wherein the timing signal is generated based on a comparison value provided by the controller. 36. The receiver unit of claim 34, wherein the timing signal is indicative of a particular number of digitized samples having been stored to the first buffer. 37. The receiver unit of claim 9, wherein a word of 32 bits or more is written to the first buffer or read from the first buffer for each buffer access. 38. The receiver unit of claim 9, wherein the first buffer is operative to store two or more packets of digitized samples. 39. The receiver unit of claim 9, wherein the first buffer is further operative to store pseudo-random noise (PN) samples. 40. The receiver unit of claim 9, wherein the processing clock has a frequency that is at least ten times higher than the sample rate, the sample rate being asynchronous with the processing clock. 41. The receiver unit of claim 9, further comprising: a data interface coupled to the first buffer, the data interface operative to receive the digitized samples, discard unnecessary samples, and assemble the samples into words suitable for efficient storage to the first buffer. 42. The receiver unit of claim 9, wherein the micro-controller is operative to instantiate a task state machine for each task being processed. 43. The receiver unit of claim 9, wherein at least one of the parameter values is programmable. 44. A method for processing a received signal in a wireless communications system, the method comprising: buffering digitized samples of a received signal in a first buffer; retrieving segments of the digitized samples from the first buffer, processing each of the retrieved segments with a particular set of parameter values; dispatching tasks for a data processor to process the retrieved segments and to process signaling data from the data processor; receiving the dispatched tasks and generating a set of control signals to direct the operation of the first buffer and the data processor to execute the dispatched tasks; latching a dispatched task and one or more parameter values to be applied for the dispatched task; providing an indicator signal based on a value stored in the latch; and receiving at least one indicator signal and the dispatched task and to generate the set of control signals. 45. The method of claim 44, wherein the processing of the segments includes despreading the retrieved segments of digitized samples with corresponding segments of PN (pseudo-random noise) despreading sequences to provide correlated samples. 46. The method of claim 45, wherein the processing further includes decovering the correlated samples with one or more channelization codes to provide decovered symbols. 47. The method of claim 46, wherein the processing further includes demodulating the decovered symbols with pilot symbols to provide demodulated symbols. 48. The method of claim 47, wherein the processing further includes accumulating the demodulated symbols from multiple signal instances to provide processed symbols. 49. The method of claim 44, wherein the digital samples are received, processed and digitized at a sample rate, and wherein the retrieved segments are processed by the data processor with a processing clock having a frequency that is higher than the sample rate, the sample rate being asynchronous with the processing clock, the method further comprising: tracking a chip rate of the digitized samples; and providing a signal used to write digitized samples to the first buffer starting at designated locations. 50. The method of claim 44 wherein the processing of the signal instances comprises: despreading the retrieved segments of the digitized samples with corresponding segments of PN (pseudo-random noise) despreading sequences to provide correlated samples decovering the correlated samples with one or more channelization codes to provide decovered symbols; demodulating the decovered symbols with pilot symbols to provide demodulated symbols; and accumulating the demodulated symbols from the multiple signal instances to provide processed symbols. 51. A method comprising: storing digitized samples comprising multiple instances of a received signal at a first buffer; at a data processor, retrieving different segments of the digitized samples one segment at a time from the first buffer, each of the retrieved different segments comprising one of the multiple signal instances; processing two or more of the retrieved different segments one segment at a time with one programmed despreading sequence to provide despread samples; decovering the despread samples with a channelization code of programmable length to provide decovered symbols; demodulating the decovered symbols to provide demodulated symbols; combining the demodulated symbols from the multiple signal instances to provide processed symbols; receiving tasks, instantiating a state machine for each task, and directing the data processor to process the retrieved multiple segments; implementing a counter to control a write address for writing digitized samples to the first buffer; and sending a signal to a controller to initiate processing of the stored samples by the data processor.