$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Methods and apparatus for compiling computer programs using partial function inlining 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0628694 (2000-07-28)
발명자 / 주소
  • Boucher,Michael
출원인 / 주소
  • Sun Microsystems, Inc.
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett &
인용정보 피인용 횟수 : 20  인용 특허 : 106

초록

A method and system makes inlining decisions that are efficient for subprograms that have significantly varying execution times over a range of variables or execution paths. A subprogram of a computer program is identified and certain execution paths of the subprogram are selectively inlined. The su

대표청구항

What is claimed is: 1. A computer-implemented method for inlining code of a computer program, comprising: identifying a subprogram of the computer program, wherein the subprogram exhibits varying execution characteristics associated with corresponding execution paths; identifying a range of variab

이 특허에 인용된 특허 (106)

  1. Adi Ofer ; Tuvia Leneman ; Natan Vishlitzky, Adaptive delay of polling frequencies in a distributed system with a queued lock.
  2. Jibbe Mahmoud K., Alterable scripting tool and method.
  3. Mehrotra Sharad ; Hetherington Ricky C. ; Wong Michelle L., Apparatus and method for handling multiple mergeable misses in a non-blocking cache.
  4. Bates Cary Lee ; Day Paul Reuben, Apparatus, program product and method of debugging utilizing a context sensitive breakpoint.
  5. Lai Michael (San Jose CA) Ng John L. (San Jose CA) Shaw Jin-Fan (San Jose CA), Array variable transformation system employing subscript table mapping to scalar loop indices.
  6. Shagam Eli ; Goral Avihu,ILX, Automatic creation of C to assembler interface.
  7. Iizawa Atsushi (Tokyo JPX) Shirota Yukari (Saitama CA JPX) Pizano Arturo (Milpitas CA), Automatic interface layout generator for database systems.
  8. Hinker, Paul J.; Boucher, Michael, Avoiding gather and scatter when calling Fortran 77 code from Fortran 90 code.
  9. Kunioka Michiko,JPX, Batch execution control programming device and method.
  10. Simser David,CAX, Bi-directional conversion library.
  11. Millind Mittal ; Martin J. Whittaker ; Gary N. Hammond ; Jerome C. Huck, COMPUTER SYSTEM THAT PROVIDES ATOMICITY BY USING A TLB TO INDICATE WHETHER AN EXPORTABLE INSTRUCTION SHOULD BE EXECUTED USING CACHE COHERENCY OR BY EXPORTING THE EXPORTABLE INSTRUCTION, AND EMULATES .
  12. Finch Richard (Austin TX) Schieve Eric (Austin TX) Vivio Joseph (Austin TX), Cache testability circuit for embedded diagnostics.
  13. Krueger Steven D. ; Shiell Jonathan H., Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal.
  14. Rouquie Gilbert J. A. (Redwood City CA), Communication between prolog and an external process.
  15. Vincent Phuoc Cao ; Lincoln A. Fajardo ; Sanjay Jinturkar ; Gang-Ryung Uh ; Yuhong Wang ; David B. Whalley, Compiler optimization techniques for exploiting a zero overhead loop mechanism.
  16. Carver Timothy M., Compiler tool set for efficiently generating and easily managing multiple program versions of different types.
  17. Henzinger Monika Hildegard ; Leung Shun-Tak Albert ; Sites Richard L. ; Vandevoorde Mark T. ; Weihl William Edward, Computer method and apparatus for analyzing program instructions executing in a computer system.
  18. Blumer Thomas P. ; Stefanik Theodore, Computer system and computer-implemented method for interpreting hypertext links in a document when including the docu.
  19. Coker Drake (691 S. Nardo ; Apt. E8 Solana Beach CA 92075), Computer system for generating SQL statements from COBOL code.
  20. Kummer David A. (Thousand Oaks CA) Rumer Robert T. (Camarillo CA), Computer system including a write protection circuit for preventing illegal write operations and a write poster with imp.
  21. Rail Peter D., Configuration file management.
  22. Eugene O'Neill IE; Una Quinlan IE; Anne G. O'Connell IE, Credit-based scheme for high performance communication between devices in a packet-based communication system.
  23. Larson Brian Ralph, Dance/multitude concurrent computation.
  24. Holt Nicholas P. (Padfield GB3), Data processing system for handling multiple independent data-driven instruction streams.
  25. Cunningham Connel G.,IEX ; O'Rourke Ferghil J.,IEX, Data processing system for sharing instances of objects with multiple processes.
  26. Ottensooser Avner Benjamin,AUX, Determination of software functionality.
  27. Sher Richard A. ; Rogers Jerry ; Wentka Mark J., Distributed memory addressing system.
  28. Tatsuo Higuchi JP; Toshiaki Tarui JP; Katsuyoshi Kitai JP; Shigeo Takeuchi JP; Tatsuru Toba JP; Machiko Asaie JP; Yasuhiro Inagami JP, EXCLUSIVE CONTROL METHOD WITH EACH NODE CONTROLLING ISSUE OF AN EXCLUSIVE USE REQUEST TO A SHARED RESOURCE, A COMPUTER SYSTEM THEREFOR AND A COMPUTER SYSTEM WITH A CIRCUIT FOR DETECTING WRITING OF AN.
  29. Hanna Christine Beth ; Levin Roy, Efficient method and apparatus for compiling and linking modules of computer code in a large software system.
  30. McInerney Peter J. (Cupertino CA) Bianchi Curtis A. (Saratoga CA), Engineering system for modeling computer programs.
  31. Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Dodson, John Steven; Guthrie, Guy Lynn; Starke, William John, Extended cache coherency protocol with a persistent "lock acquired" state.
  32. Rust Scott ; Bellin Jon ; Grey James, Instrumentation system and method including an improved driver software architecture.
  33. Bird Ronald W. (Kent WA) Shaffer David K. (Seattle WA), Integrated certification-calibration system for a testing system having multiple test instruments.
  34. DeMaster Jerry D., Java native interface code generator.
  35. Albonesi David H., Mechanism for dynamically adapting the complexity of a microprocessor.
  36. Steely ; Jr. Simon C. ; Sharma Madhumitra ; Gharachorloo Kourosh ; Van Doren Stephen R., Mechanism for reducing latency of memory barrier operations on a multiprocessor system.
  37. Wentka Mark J. ; Sher Richard A., Memory interface device.
  38. Ault Donald F. ; Fischer John F. ; Miller Eric T., Method and apparatus for allocating and freeing storage utilizing multiple tiers of storage organization.
  39. Schofield Andrew,CHX, Method and apparatus for asynchronously calling and implementing objects.
  40. Eustace Robert A. (Redwood City CA) Monier Louis (Redwood City CA), Method and apparatus for checking validity of memory operations.
  41. Richardson John, Method and apparatus for client managed flow control on a limited memory computer system.
  42. Fromme Brian D. (Fort Collins CO), Method and apparatus for computer program encapsulation.
  43. Olsen Bruce A. ; Wun Le-chun ; Hwu Wen-mei, Method and apparatus for debugging of optimized code.
  44. Rajiv Mirani ; Bruce A. Olsen ; Harish Patil, Method and apparatus for debugging of optimized code using emulation.
  45. Schofield Andrew,CHX, Method and apparatus for describing an interface definition language-defined interface, operation, and data type.
  46. Swanson Jim A. (Dallas/Fort Worth Airport TX), Method and apparatus for developing scripts that access mainframe resources that can be executed on various computer sys.
  47. Rodgers Scott D. (Hillsboro OR) Tiruvallur Keshavan K. (Hillsboro OR) Rhodehamel Michael W. (Beaverton OR) Konigsfeld Kris G. (Portland OR) Glew Andrew F. (Hillsboro OR) Akkary Haitham (Portland OR) , Method and apparatus for performing operations based upon the addresses of microinstructions.
  48. Andrews Kristy A. ; Del Vigna Paul ; Molloy Mark E., Method and apparatus for reconciling conflicting translations by factoring and parameterizing differences.
  49. Lawrence Roger P. (Cupertino CA) Dance John R. (Cupertino CA), Method and apparatus of incrementally linking components of a modeled computer program.
  50. Ungar David, Method and apparatus of translating and executing native code in a virtual machine environment.
  51. Whitten Thomas G., Method and computer program product for generating a computer program product test that includes an optimized set of co.
  52. Kranich, Uwe; Christie, David S., Method and mechanism for speculatively executing threads of instructions.
  53. Perkins David Theodore ; Foster Gregory Allen, Method and system for compiling management information base specifications.
  54. Brian D. Koblenz ; Allan Porterfield ; Burton J. Smith, Method and system for memory allocation in a multiprocessing environment.
  55. Larsen Troy Dale ; Randolph Jack Chris ; Wottreng Andrew Henry, Method and system for performance per-thread monitoring in a multithreaded processor.
  56. Christopher ; Jr. Kenneth W. (Lighthouse Point FL) Huynh Khoa D. (Miami FL) Roarabaugh Virginia M. (Boca Raton FL) Waldron ; III Theodore C. (Sunrise FL), Method and system for utilizing benign fault occurrence to measure interrupt-blocking times.
  57. Kanamori Atsushi, Method and system of custom marshaling of inter-language parameters.
  58. Fadi Y. Busaba, Method for binary to decimal conversion.
  59. Ishizaki Kazuaki,JPX ; Komatsu Hideaki,JPX ; Ogasawara Takeshi,JPX, Method for executing communication between processors in parallel computer.
  60. Ghahramani Bahador, Method for measuring the usability of a system and for task analysis and re-engineering.
  61. Zuravleff William K. ; Semmelmeyer Mark ; Robinson Timothy ; Furman Scott, Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the.
  62. Cheng Lei ; Eckert Thomas F. ; Wisor Michael T., Method for testing the non-cacheable region functioning of a cache memory controller.
  63. Kolawa Adam K. ; Salvador Roman,ESX ; Hicken Wendell T. ; Strickland Bryan R., Method using a computer for automatically instrumenting a computer program for dynamic debugging.
  64. Richardson John L., Method, system and computer program product for profiling thread virtual memory accesses.
  65. Paul Hinker ; Shaun Dennie, Methods, apparatus, and articles of manufacture for analyzing memory use.
  66. Bradley Lewis ; Jeremy Week ; Michael Boucher ; Shaun Dennie, Methods, systems, and articles of manufacture for analyzing performance of application programs.
  67. Yamagami Nobuhiko,JPX, Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data.
  68. Kyle David G. ; Lee Sherman, Microprocessor with automatic name generation including performance indication.
  69. Maruyama Teruyuki,JPX, Multiprocessor system memory unit with split bus and method for controlling access to the memory unit.
  70. Zuravleff William K. ; Semmelmeyer Mark ; Robinson Timothy ; Furman Scott, Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing.
  71. Notess Mark H. (Ft. Collins CO) Warren Scott J. (Timnath CO) Heiserman Tammy (Ft. Collins CO) Kingdom Michael A. (Loveland CO), Object-action user interface management system.
  72. Thompson John Alan, Object-oriented method and apparatus for creating a makefile.
  73. De Borst Jeroen,DEX ITX 61348 ; Bonham Peter,DEX ITX 61352 ; Erlenkoetter Ansgar,DEX ITX 61267 ; Schofield Andrew,DEX ITX CH-6330 ; Kaeser Reto,CHX ITX Ch-8968, Object-oriented method and apparatus for information delivery.
  74. Wendorf, James W.; Rath, Kamlesh; Verma, Dinesh, Operating system for use with protection domains in a single address space.
  75. Hiroaki Sato JP, Optimized program code generator, a method for compiling a source text and a computer-readable medium for a processor capable of operating with a plurality of instruction sets.
  76. Honda Kazushi,JPX, Optimized variable allocation method, optimized variable allocation system and computer-readable memory containing an optimized variable allocation program.
  77. Flaat Christopher A., Parameterized packaging system for programming languages.
  78. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Performance monitor and method for performance monitoring within a data processing system.
  79. Flynn William Thomas ; Randolph Jack Chris ; Larsen Troy Dale, Performance monitoring of thread switch events in a multithreaded processor.
  80. Nikhil Rishiyur S. (Arlington MA) Arvind (Arlington MA), Pipelined processor with fork, join, and start instructions using tokens to indicate the next instruction for each of mu.
  81. Brandle Richard T. (Marietta GA) Goodliffe Don L. (Dunwoody GA) Keith Donald E. (Peachtree City GA) Robinette Randy A. (Acworth GA) Sizemore Robert C. (Acworth GA) Smithwick Garry J. (Alpharetta GA) , Procedure call interface.
  82. James David V. (Palo Alto CA), Processor with sequences of processor instructions for locked memory updates.
  83. Heisch Randall Ray (Austin TX), Profile-based optimizing postprocessors for data references.
  84. Tomokazu Kanamaru JP; Nobuki Tominaga JP, Program conversion apparatus.
  85. Fromm Eric C., Recursive address centrifuge for distributed memory massively parallel processing systems.
  86. Carr Richard W. ; Garrard Brian,GB2 ; Mosher ; Jr. Malcolm, Remote duplicate database facility with improved throughput and fault tolerance.
  87. Stubbs David D. (Portland OR), Signal viewing instrumentation control system.
  88. Boyle Douglas B. ; Koford James S. ; Jones Edwin R. ; Scepanovic Ranko ; Rostoker Michael D., Single chip integrated circuit distributed shared memory (DSM) and communications nodes.
  89. Poulsen David K. ; Petersen Paul M. ; Shah Sanjiv M., Software implemented method for automatically validating the correctness of parallel computer programs.
  90. Hayter, Mark D.; Rowlands, Joseph B., Source controlled cache allocation.
  91. Heisch Randall Ray, System and method for acquiring high granularity performance data in a computer system.
  92. Mitchell Bob ; Andrade Hugo ; Pathak Jogen ; DeKey Samson ; Shah Abhay ; Brower Todd, System and method for creating resources in an instrumentation system.
  93. Chen James N. (Austin TX) Ross Joseph C. (Georgetown TX), System and method for maintaining performance data in a data processing system.
  94. Chen Yih-Farn Robin (Bridgewater NJ) Rosenblum David Samuel (Maplewood NJ) Vo Kiem-Phong (Berkeley Heights NJ), System and method for selecting test units to be re-run in software regression testing.
  95. Gillies David M. ; Ju Dz-ching, System and method for solving general global data flow predicated code problems.
  96. Kukol Peter (Aptos CA), System and methods for optimizing object-oriented compilations.
  97. Brooks Gary S., System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses.
  98. Andrews Kristy A. ; Del Vigna Paul ; Molloy Mark E., System for ensuring the accuracy of file structures in a source-to-source computer program translator.
  99. Srivastava Amitabh (Menlo Park CA) Eustace Robert A. (Redwood City CA), System for monitoring computer system performance.
  100. Reeve Christopher L. (18 Salisbury Rd. Brookline MA 02146) Shavit Tani (One Seaborn Pl. Lexington MA 02173) Rothnie ; Jr. James B. (47 Monmouth St. Brookline MA 02146) Peters Timothy G. (11 Wilbur St, System for parallel processing that compiles a filed sequence of instructions within an iteration space.
  101. Jack Martin L. (Merrimac NH) Gumbel Richard T. (Windham NH), System for selectively converting plurality of source data structures through corresponding source intermediate structur.
  102. Lane Harriet, Technology regression and verification acceptance method.
  103. Ranganathan Kumar, Thread performance analysis by monitoring processor performance event registers at thread switch.
  104. Parady Bodo, Thread switch on blocked load or store using instruction thread field.
  105. Kim Thomas Dongsuk ; Hawthorne Seth Gordon ; Kosinski Joseph Stanley, Tool and method for diagnosing and correcting errors in a computer program.
  106. Shenoy Anil K. (Los Altos CA) D\Angelo Vincent (Los Gatos CA) Utz ; Jr. Walter J. (San Jose CA), Various possible execution paths measurement and analysis system for evaluating before writing source codes the efficien.

이 특허를 인용한 특허 (20)

  1. Ryan, Anthony Robert; Carrick, James, Automatic minimal build dependency determination and building an executable with source code.
  2. Liu, Yaxun; Tanase, Ilie G.; Tiotto, Ettore, Compiler optimization based on collectivity analysis.
  3. Liu, Yaxun; Tanase, Ilie G.; Tiotto, Ettore, Compiler optimization based on collectivity analysis.
  4. Smith, Frederick Mattsson; Bottema, Alexander Jean-Claude; Ren, Yao, Context-sensitive compiler directives.
  5. Nistler,John Gerard; Schroeder,Mark Douglas, Determining how many class-type checks to inline.
  6. Sage, Robert G., Executable code generated from common source code.
  7. Miller, Swaha Das; Rossie, Jr., Jonathan Gregory; Taylor, Jamie, Message inlining.
  8. Vick, Christopher A.; Valencia, Andres, Method for controlling inlining in a code generator.
  9. Doyle, Patrick R.; Gartley, James I. A.; Inglis, Derek B.; Sundaresan, Vijay, Partial inlining with software based restart.
  10. Fine, Shai; Ur, Shmuel; Ziv, Avi; Rushton, Simon, Probabilistic regression suites for functional verification.
  11. Dickenson, Marc Alan, Self-optimizable code for optimizing execution of tasks and allocation of memory in a data processing system.
  12. Schmidt, William J., Strength reduction compiler optimizations.
  13. Schmidt, William J., Strength reduction compiler optimizations.
  14. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  15. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  16. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  17. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  18. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  19. Schmidt, William J., Strength reduction compiler optimizations for operations with unknown strides.
  20. Liu,James; Pillutla,Raghavender; Yen,Chien Hua; Mac,Timothy; Yacoub,Yousef, Systems and methods for software performance tuning.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로