Pulse interval to voltage converter and conversion method thereof
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0708645
(2004-03-17)
|
우선권정보 |
TW-92113765 A(2003-05-21) |
발명자
/ 주소 |
- Kuo,Terry B. J.
- Yang,Cheryl C. H.
|
출원인 / 주소 |
|
대리인 / 주소 |
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인용정보 |
피인용 횟수 :
6 인용 특허 :
7 |
초록
▼
A Pulse Interval to Voltage Converter (PIVC) and conversion method thereof is revealed. The PIVC comprises a clock generator, a counter, a latch, a digital-to-analog converter (DAC), a delay unit, a frequency regulator and an underflow protection unit. New components, such as the delay unit, the fre
A Pulse Interval to Voltage Converter (PIVC) and conversion method thereof is revealed. The PIVC comprises a clock generator, a counter, a latch, a digital-to-analog converter (DAC), a delay unit, a frequency regulator and an underflow protection unit. New components, such as the delay unit, the frequency regulator and the underflow protection unit, are incorporated into the present invention, unlike the conventional art. The delay unit is intended for the programming of the default duration of delay, so as to delay the time for the counter to reset to zero, and in consequence regulate the baseline of the output voltage. The frequency regulator can regulate the clock generation frequency of the clock generator, so as to regulate the resolution of the output voltage. The underflow protection unit turns back external signals while the delay unit is operating, so as to minimize interference from noise.
대표청구항
▼
What is claimed is: 1. A pulse interval to voltage converter, comprising: a delay unit for delaying an input pulse signal; a counter connected to the delay unit, wherein the count of the counter is reset to zero when the counter receives the input pulse signal; a latch for locking the count of the
What is claimed is: 1. A pulse interval to voltage converter, comprising: a delay unit for delaying an input pulse signal; a counter connected to the delay unit, wherein the count of the counter is reset to zero when the counter receives the input pulse signal; a latch for locking the count of the counter before the counter is reset; a digital-to-analog converter for converting the count of the latch into an analog signal; and a synchronization unit for synchronizing the input pulse signal and a clock signal. 2. The pulse interval to voltage converter of claim 1, further comprising a frequency regulator for regulating a clock frequency of a clock generator. 3. The pulse interval to voltage converter of claim 1, further comprising a clock generator for generating clock signals. 4. The pulse interval to voltage converter of claim 2, wherein the frequency regulator is a frequency divider. 5. The pulse interval to voltage converter of claim 1, further comprising an underflow protection circuit for ignoring the count of the counter when the counter exceeds a predetermined value. 6. The pulse interval to voltage converter of claim 1, further comprising an overflow protection circuit for ignoring the count of the counter when the counter exceeds a predetermined value. 7. The pulse interval to voltage converter of claim 1, further comprising a conditioning unit for regulating the input pulse signal to conform to transistor-transistor logic (TTL) specification. 8. The pulse interval to voltage converter of claim 1, wherein the delay unit comprises two counters of integrated circuit (IC) type and a NOR gate. 9. The pulse interval to voltage converter of claim 8, wherein the delay unit further comprises four digital dials, the digital input of each counter of IC type is incorporated with two of the digital dials for setting. 10. The pulse interval to voltage converter of claim 4, wherein the frequency divider comprises two counters of IC type, a NOR gate and an inverter. 11. The pulse interval to voltage converter of claim 10, wherein the frequency divider further comprises four digital dials for setting. 12. A pulse interval to voltage conversion method, comprising: (a) delaying an input pulse signal; (b) calculating the time between the input pulse signal and its preceding delayed input pulse signal; (c) converting the time into a digital voltage; and (d) converting the digital voltage into an analog voltage, wherein other input pulse signals are ignored when the input pulse signal is being delayed. 13. The pulse interval to voltage conversion method of claim 12, wherein the time calculation in step (b) is based on the number of clock cycles between the input pulse signal and its preceding delayed input pulse signal. 14. The pulse interval to voltage conversion method of claim 12, further comprising a step of decreasing the frequency of a clock signal.
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