초록 ▼

Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the fi

Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

대표청구항 ▼

What is claimed is: 1. An integrated circuit, comprising: a dual-polarity non-volatile memory cell; and a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch, further the bias voltage

What is claimed is: 1. An integrated circuit, comprising: a dual-polarity non-volatile memory cell; and a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch, further the bias voltage generator connects to a first charge storage component in the dual-polarity non-volatile memory cell via the first switch and to a second charge storage component in the dual-polarity non-volatile memory cell via a second switch. 2. The integrated circuit of claim 1, wherein the dual-polarity non-volatile memory cell couples to its own bias generator. 3. The integrated circuit of claim 1, wherein the first switch is a transistor or a transfer gate. 4. The integrated circuit of claim 1, wherein the dual-polarity non-volatile memory cell is included in an embedded memory. 5. An integrated circuit, comprising: a dual-polarity non-volatile memory cell; a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch; and a third switch and a fourth switch to connect the dual-polarity non-volatile memory cell to an external bias voltage generator. 6. The integrated circuit of claim 5, wherein the external bias voltage generator is operable to provide at least one of a plurality of discrete voltage levels and a voltage level that can vary throughout a range. 7. An integrated circuit, comprising: a dual-polarity non-volatile memory cell; a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch; and a sense amplifier, wherein the test circuit to determine a sense error of the sense amplifier connected between a first charge storage component and a second charge storage component in the dual-polarity non-volatile memory cell. 8. An integrated circuit, comprising: a dual-polarity non-volatile memory cell; a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch; and a differential sense amplifier, wherein the test circuit to determine distribution of sense error of two or more differential sense amplifiers. 9. An integrated circuit, comprising: a dual-polarity non-volatile memory cell, wherein a first charge storage component in the dual-polarity non-volatile memory cell is tested to a positive polarity and a second charge storage component in the dual-polarity non-volatile memory cell is tested to a negative polarity; and a test circuit having a bias voltage generator and a first switch, the bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch. 10. A machine readable medium that stores data representing an integrated circuit, comprising: a dual-Polarity non-volatile memory cell; a test circuit having a bias voltage generator and a first switch, the bias voltage generator connects to the dual-polarity non-volatile memory cell via the first switch, wherein the bias voltage generator is internal to the integrated circuit; and a memory compiler to provide a layout utilized to generate one or more lithographic masks used in the fabrication of the dual-polarity non-volatile memory cell and the test circuit. 11. The machine readable medium of claim 10, wherein the one or more lithographic masks are utilized during a Complementary Metal Oxide Semiconductor logic process employing equal or less than 1.0 micron technology. 12. A machine readable medium that stores data representing an integrated circuit, comprising: a dual-polarity non-volatile memory cell; a test circuit having a bias voltage generator and a first switch, the bias voltage generator connects to the dual-polarity non-volatile memory cell via the first switch, wherein the bias voltage generator is internal to the integrated circuit, further the bias voltage generator connects to a first charge storage component in the dual-polarity non-volatile memory cell via the first switch and to a second charge storage component in the dual-polarity non-volatile memory cell via a second switch. 13. A method, comprising: connecting an external bias voltage generator to a dual-polarity non-volatile memory cell; supplying a plurality of test voltage levels with the external bias voltage generator to the dual-polarity non-volatile memory cell; and determining a sense error of a differential sense amplifier connected to the dual-polarity non-volatile memory cell. 14. The method of claim 13, further comprising: determining the sense error results based on an output of the differential sense amplifier connected to the dual-polarity non-volatile memory cell. 15. The method of claim 13, further comprising: supplying a range of analog voltages with the external bias voltage generator when supplying the plurality of test voltage levels to determine the sense error. 16. The method of claim 13, further comprising: determining an offset bias voltage of a first portion of the dual-polarity non-volatile memory cell. 17. The method of claim 16, further comprising: incrementally stepping through a plurality of discrete voltage levels to determine the offset bias voltage of the first portion of the dual-polarity non-volatile memory cell. 18. An apparatus, comprising: means for connecting an external bias voltage generator to a dual-polarity non-volatile memory cell; means for supplying a plurality of test voltage levels with the external bias voltage generator to the dual-polarity non-volatile memory cell; and means for determining a sense error of a differential sense amplifier connected to the dual-polarity non-volatile memory cell.