초록 ▼

A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sa

A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.

대표청구항 ▼

What is claimed is: 1. A communication circuit communication circuit, comprising: an all-digital loop circuit configured to output a sample rate control signal to be a function of a frequency of a reference signal received by the communication circuit; a variable-ratio sample rate filter that chan

What is claimed is: 1. A communication circuit communication circuit, comprising: an all-digital loop circuit configured to output a sample rate control signal to be a function of a frequency of a reference signal received by the communication circuit; a variable-ratio sample rate filter that changes a sample rate of an output digital data stream relative to a sample rate of an input digital data stream in response to the sample rate control signal received from the all-digital loop circuit; an analog-to-digital converter coupled to the variable-ratio sample rate filter; and a fixed clock coupled to the analog-to-digital converter to substantially fix a sampling rate of the analog-to-digital converter. 2. The communication circuit claimed in claim 1 wherein the variable-ratio sample rate filter comprises a digital decimation filter. 3. The communication circuit claimed in claim 2 wherein the decimation filter comprises an ADSL decimation filter. 4. The communication circuit claimed in claim 2 wherein the decimation filter comprises a POTS decimation filter. 5. The communication circuit claimed in claim 1 wherein the communication circuit further comprises a second variable-ratio sample rate filter, and a digital-to-analog converter coupled to both the second variable-ratio sample rate filter and the fixed clock to substantially fix a sampling rate of the digital-to-analog converter. 6. The communication circuit claimed in claim 5 wherein the variable-ratio sample rate filter comprises a decimation filter, and the second variable-ratio sample rate filter comprises an interpolation filter. 7. The communication circuit claimed in claim 6 wherein the decimation filter comprises an ADSL decimation filter and the interpolation filter comprises an ADSL interpolation filter. 8. The communication circuit claimed in claim 6 wherein the decimation filter comprises a POTS decimation filter and the interpolation filter comprises a POTS interpolation filter. 9. A communication circuit, comprising: an all-digital loop circuit configured to output a sample rate control signal to be a function of a frequency of a reference signal received by the communication circuit; and a variable-ratio sample rate filter that changes a sample rate of an output digital data stream relative to a sample rate of an input digital data stream in response to the sample rate control signal received from the all-digital loop circuit, wherein the reference signal comprises a pilot tone signal. 10. A communication circuit, comprising: an all-digital loop circuit configured to output a sample rate control signal to be a function of a frequency of a reference signal received by the communication circuit; a variable-ratio sample rate filter that changes a sample rate of an output digital data stream relative to a sample rate of an input digital data stream in response to the sample rate control signal received from the all-digital loop circuit; a digital-to-analog converter coupled to the variable-ratio sample rate filter; and a fixed clock coupled to the digital-to-analog converter to substantially fix a sampling rate of the digital-to-analog converter. 11. The communication circuit claimed in claim 10 wherein the variable-ratio sample rate filter comprises an interpolation filter, and the interpolation filter comprises an ADSL interpolation filter. 12. The communication circuit claimed in claim 10 wherein the variable-ratio sample rate filter comprises an interpolation filter, and the interpolation filter comprises a POTS interpolation filter.