초록 ▼

A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on respectively different layer types. In this manner, the at least two different wiring forms can be ind

A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on respectively different layer types. In this manner, the at least two different wiring forms can be individually and jointly analyzed.

대표청구항 ▼

We claim: 1. A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the steps of: assigning a respectively different layer type in a layout representation to each of the different wiring forms,

We claim: 1. A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the steps of: assigning a respectively different layer type in a layout representation to each of the different wiring forms, when carrying out graphical layout design; distinguishing the two different wiring forms as a short-range wiring form and a wide-range wiring form that can be automatically identified in the layout representation as the respectively different layer types, the wide-range wiring form substantially containing wirings for signal and supply lines for a plurality of function blocks, and the short-range wiring form substantially containing wirings of individual components within a function block; illustrating in the layout representation the wide-range wiring form using an automatic wiring tool; and illustrating in the layout representation the short-range wiring form based on a macro level and largely manually. 2. The fabrication method according to claim 1, which comprises: assigning a first minor layer type to the wide-range wiring form on the metallization plane; and assigning a second minor layer type to the short-range wiring form on the metallization plane in macros. 3. A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the steps of: assigning a respectively different layer type in a layout representation to each of the different wiring forms, when carrying out graphical layout design; and storing the respectively different layer types in a computer in respectively assigned different data formats. 4. A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the steps of: distinguishing the two different wiring forms as a short-range wiring form and a wide-range wiring form that can be automatically identified in a representation thereof, the wide-range wiring form substantially containing wirings for signal and supply lines for a plurality of function blocks, and the short-range wiring form substantially containing wirings of individual components within a function block; assigning a respectively different layer type in a layout representation to each of the different wiring forms, when carrying out graphical layout design, by the steps of: illustrating the wide-range wiring form using an automatic wiring tool; illustrating the short-range wiring form based on a macro level and largely manually; and automatically manipulating structures stored as data during a chip design by carrying out a manipulation for the wide-range wiring form and the short-range wiring form with in each case specific values depending on the respectively defined layer types. 5. A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane, which comprises the steps of: distinguishing the two different wiring forms as a short-range wiring form and a wide-range wiring form that can be automatically identified in a representation thereof, the wide-range wiring form substantially containing wirings for signal and supply lines for a plurality of function blocks, and the short-range wiring form substantially containing wirings of individual components within a function block; assigning a respectively different layer type in a layout representation to each of the different wiring forms, when carrying out graphical layout design, by the steps of: illustrating in the layout the wide-range wiring form using an automatic wiring tool; illustrating in the layout the short-range wiring form based on a macro level and largely manually; and automatically checking technological specifications for a physical chip design using software by checking structures stored as data for the short-range wiring form and for the wide-range wiring form with in each case specific values depending on the respectively defined layer types.