초록 ▼

A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a pl

A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.

대표청구항 ▼

What is claimed is: 1. A configurable address generation circuit, comprising: an addressing sequence circuit comprising a plurality of counting circuits and at least one comparator coupled to the plurality of counting circuits; and programmable logic coupled to the addressing sequence circuit, the

What is claimed is: 1. A configurable address generation circuit, comprising: an addressing sequence circuit comprising a plurality of counting circuits and at least one comparator coupled to the plurality of counting circuits; and programmable logic coupled to the addressing sequence circuit, the programmable logic configuring the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the configurable address generation circuit to meet one of a plurality of address generation requirements, the programmable logic being programmed so that the configurable address generation circuit provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses. 2. A configurable address generation circuit as defined in claim 1, wherein the plurality of counting circuits comprises at least one counter. 3. A configurable address generation circuit as defined in claim 1, wherein the plurality of counting circuits comprises at least one linear feedback shift register. 4. A configurable address generation circuit as defined in claim 1, wherein the at least one comparator is used to detect different addressing conditions. 5. A configurable address generation circuit as defined in claim 1, wherein the programmable logic can be programmed so that the address generation circuit functions as a stack pointer. 6. A configurable address generation circuit as defined in claim 5, wherein a counting circuit of the plurality of counting circuits comprises a counter which can count up and/or down and is reloadable. 7. A configurable address generation circuit as defined in claim 1, wherein the addressing sequence circuit includes first and second counters and the programmable logic is programmed such that the first and second counters can address a MAC FIR filter. 8. A configurable address generation circuit as defined in claim 7, wherein the first counter addresses coefficients of the FIR filter and the second counter addresses data sample addresses of the MAC FIR filter. 9. A configurable address generation circuit as defined in claim 1, further comprising a comparator coupled to first and second counters, the comparator comparing the write addresses from the first counter and the read addresses from the second counter and providing a full signal when the write address is one less than the read address. 10. A configurable address generation circuit as defined in claim 9, wherein the programmable logic is programmed such that the first and second counters address a First-In First-Out circuit. 11. A configurable address generation circuit as defined in claim 1, wherein the addressing sequence circuit is coupled to a Block Random Access Memory (BRAM) located within a Field Programmable Gate Array (FPGA). 12. An integrated circuit, comprising: an addressing sequence circuit comprising a plurality of counting circuits and a comparator coupled to the plurality of counting circuits; programmable logic coupled to the addressing sequence circuit, the programmable logic used to configure the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the integrated circuit, the programmable logic being programmed so that the integrated circuit provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses; and a memory coupled to the addressing sequence circuit. 13. An integrated circuit as defined in claim 12, wherein the memory comprises a Block Random Access Memory. 14. An integrated circuit as defined in claim 13, wherein the integrated circuit comprises a Field Programmable Gate Array (FPGA). 15. An integrated circuit as defined in claim 14, wherein the addressing sequence circuit comprises hard-wired circuits. 16. An integrated circuit as defined in claim 12, wherein the addressing sequence circuit comprises hard-wired circuits and the programmable circuitry configures the hard-wired circuits to meet different address generation requirements. 17. An integrated circuit as defined in claim 16, wherein the integrated circuit comprises a Field Programmable Gate Array (FPGA). 18. A Field Programmable Gate Array (FPGA), comprising: an addressing sequence circuit comprising a plurality of counting circuits and a comparator coupled to the plurality of counting circuits; and programmable logic coupled to the addressing sequence circuit, the programmable logic configuring the addressing sequence circuit in response to proarammable bits of a configuration bit file coupled to the FPGA in order to provide addressing to different types of circuits, the proarammable logic being programmed so that the FPGA provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses. 19. A FPGA as defined in claim 18, further comprising: a memory coupled to the addressing sequence circuit. 20. A FPGA as defined in claim 19, wherein the addressing sequence circuit comprises hard-wired circuitry. 21. A FPGA as defined in claim 20, wherein the programmable logic allows for the addressing sequence circuit to be configured to address different types of circuits. 22. An integrated circuit, comprising: an addressing sequence circuit, comprising a means for counting and a means for comparing; and a means for configuring the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the integrated circuit in order to provide addressing to different types of circuits, the means for configuring being programmed so that the integrated circuit provides address generation wherein a first counting circuit of the means for counting provides write addresses and a second counting circuit of the means for counting circuits provides read addresses.