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A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory provided external to the processor. In the signal processor, the process execution unit automatically re

A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory provided external to the processor. In the signal processor, the process execution unit automatically returns to a start point of a loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory.

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What is claimed is: 1. A signal processor comprising: a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory; and an external memory provided external to the processor, wherein the process execution unit automa

What is claimed is: 1. A signal processor comprising: a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory; and an external memory provided external to the processor, wherein the process execution unit automatically returns to a start point of loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory and the process execution unit comprises: an instruction decoding/issuing unit configured to receive an execution instruction; a register file configured to receive a register number specifying a signal from the instruction decoding/issuing unit; a prefetch execution control unit configured to receive a prefetch instruction execution signal from the instruction decoding/issuing unit and register content output data from the register file; an external memory control unit configured to receive an external memory control instruction signal from the prefetch execution control unit; a cache memory control unit configured to receive a cache memory control instruction signal from the prefetch execution control unit; and a data process unit coupled to the external memory control unit and to the cache memory control unit, and the prefetch execution control unit comprises: a temporary memory configured to receive the register content output data from the register file; a prefetch address operational generator/comparator unit which receives data from the temporary memory; a prefetch block number operation unit configured to receive prefetch block number data different from the data from the temporary memory and transmits/receives a first control signal to/from the prefetch address operational generator/comparator unit; and an external memory access number status decision unit configured to receive an external memory control instruction response signal from the external memory control unit receiving external memory access address information transmitted from the prefetch address operational generator/comparator unit, and transmits a second control signal to the prefetch address operational generator/comparator unit. 2. The signal processor of claim 1, wherein the temporary memory unit comprises: a loop start address data area storing loop start address data; a loop end offset data area storing loop end offset data; a prefetch start address data area storing prefetch start address data; a stride address data area storing stride address data; a block size data area storing block size data; and a prefetch block number data area storing prefetch block number data. 3. A computer implemented prefetch instruction method comprising: determining a loop start address and a loop end offset so as to assign a loop prefetch applied area, a loop prefetch not-applied area, and excluded data area in address data area in an external memory; specifying a prefetch start address in the loop prefetch not-applied area; reading out discrete block data by a block size in the loop prefetch not-applied area, by specifying a predetermined stride address from the prefetch start address; automatically returning to the loop start address on reaching an end of the loop prefetch applied area; and connecting the loop end prefetch data and the loop start prefetch data continuously at the end of loop-type data. 4. The method of claim 3, further comprising reading out discrete block data by the block size in the loop prefetch applied area in the address data area, by specifying the predetermined stride address from the prefetch start address. 5. A computer implemented prefetch instruction method comprising: setting a sum of a transfer data number and an incremental part of data transfer as a new number of transfer data; setting a sum of a transfer address and an address of the incremental part of data transfer as a new transfer address; judging whether the new transfer address is larger than a sum of a loop start address and a loop end offset; judging whether a block size of block data is equal to the new transfer data number if the new transfer address is smaller than the sum of the loop start address and the loop end offset; deleting backward data overflowing from a loop end and storing remaining forward data in a buffer if the new transfer address is larger than the sum of the loop start address and the loop end offset; obtaining data represented by a value obtained by subtracting a remaining part of the data transfer from the incremental part of the data transfer at a position of the loop start address and writing the data in a free space area of the buffer; and setting a sum of the new transfer address and an address corresponding to a value obtained by subtracting the remaining part of the data transfer from the incremental part of the data transfer as a further new transfer address. 6. The prefetch instruction method of claim 5, further comprising: storing the read-out data in a cache from the buffer if the block size is not equal to the new transfer data number; setting a value obtained by adding one to a transfer block number as a new transfer block number if the block size is equal to the new transfer data number; judging whether a prefetch block number is equal to the new transfer block number; finishing prefetch transfer if the prefetch block number is equal to the new transfer block number; and setting a sum of the new transfer address and a value obtained by subtracting the block size from the stride address as a block lead address if the prefetch block number is not equal to the new transfer block number. 7. A computer program product for executing an application on a signal processor, the computer program product comprising: instructions configured to set a sum of a transfer data number and an incremental part of data transfer as a new transfer data number; instructions configured to set a sum of a transfer address and an address of the incremental part of the data transfer as a new transfer address; instructions configured to judge whether the new transfer address is larger than a sum of a loop start address and a loop end offset; instructions configured to judge whether a block size is equal to the new transfer data number if the new transfer address is smaller than the sum of the loop start address and the loop end offset; instructions configured to delete backward data overflowed from a loop end and storing remaining forward data in a buffer if the new transfer address is larger than the sum of the loop start address and the loop end offset; instructions configured to obtain data represented by a value obtained by subtracting a remaining part of the data transfer from the incremental part of the data transfer at a position of a loop start address and write the data in a free space area of the buffer; and instructions configured to set a sum of the new transfer address and an address corresponding to a value obtained by subtracting the remaining part of the data transfer from the incremental part of the data transfer as a further new transfer address. 8. The computer program product of claim 7, further comprising: instructions configured to store the read-out data in a cache from a buffer if the block size is not equal to the new transfer data number; instructions configured to set a value obtained by adding one to a transfer block number as a new transfer block number if the block size is equal to the new transfer data number; instructions configured to judge whether a prefetch block number is equal to the new transfer block number; instructions configured to finish prefetch transfer if the prefetch block number is equal to the new transfer block number; and instructions configured to set a sum of the new transfer address and a value obtained by subtracting a block size from a stride address as a block lead address if the prefetch block number is not equal to the new transfer block number.