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A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform dat

A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

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What is claimed is: 1. A microprocessor that performs processing according to an instruction fetched from a memory, comprising: a calculation circuit that (i) includes partial calculation circuits which each perform partial data calculation, upon receiving a clock signal, and (ii) is operable to pe

What is claimed is: 1. A microprocessor that performs processing according to an instruction fetched from a memory, comprising: a calculation circuit that (i) includes partial calculation circuits which each perform partial data calculation, upon receiving a clock signal, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation circuits are to perform data calculation, wherein the partial calculation circuits, except for a partial calculation circuit that performs data calculation on a most significant bit of the N bits, are each operable to output a carry bit signal indicating an overflow occurring during data calculation, the calculation circuit includes a carry bit signal transmitting unit that inputs to each of all the partial calculation circuits except for a partial calculation circuit that performs data calculation on a least significant bit of the N bits, a carry bit signal outputted from a partial calculation circuit that performs data calculation on a number of less significant bits than the particular partial calculation circuit to which such a carry bit signal is to be inputted does; a bit width selecting unit operable to select a bit width mode that designates a certain number of bits on which data calculation is to be performed; an execution controlling unit operable to, if the fetched instruction is an instruction for data calculation, control the calculation circuit to perform data calculation; an operation controlling unit operable to, when the execution controlling unit controls the calculation circuit to perform data calculation, (i) have all the partial calculation circuits operate, in a case where the bit width selecting unit selects a first bit width mode designating N bits, and (ii) suspend operation of a predetermined number of the partial calculation circuits, and have the rest of the partial circulation circuits operate, in a case where the bit width selecting unit selects a second bit width mode designating less than N bits; and a carry bit signal inhibiting unit operable to, in a case where the bit width selecting unit selects the second bit width mode, inhibit the carry bit signal transmitting unit from inputting a carry bit signal to the predetermined number of the partial calculation circuits to which the supply of a clock signal is suspended by the operation controlling unit, wherein the operation controlling unit (i) in a case where the bit width selecting unit selects the first bit width mode, supplies a clock signal to each of all the partial calculation circuits, and (ii) in a case where the bit width selecting unit selects the second bit width mode, suspends the supply of a clock signal to a predetermined number of the partial calculation circuits, and supplies a clock signal to each of the rest of the partial calculation circuits. 2. The microprocessor of claim 1, wherein: the partial calculation circuits each include a calculator and a bit data obtaining circuit, the calculator performing data calculation on a number of bits of data supplied, and the bit data obtaining circuit, upon receiving a clock signal, obtaining the number of bits of data from one or more data buses and supply to the calculator, the number being specific to each of the partial calculation circuits, and the operation controlling unit supplies a clock signal to each of the partial circulation circuits by supplying a clock signal to each of the bit data obtaining circuits. 3. The microprocessor of claim 1, further comprising: a clock frequency controlling unit operable to (i) control the operation controlling unit to supply the clock signal of a first frequency to each of the partial calculation circuits, in a case where the bit width selecting unit selects the first bit width mode, and (ii) control the operation controlling unit to supply the clock signal of a second frequency, which is higher than the first frequency, to each of the partial calculation circuits, in a case where the bit width selecting unit selects the second bit width mode. 4. The microprocessor of claim 1, further comprising: a voltage controlling unit operable to control a voltage level so as to (i) impress a voltage of a first voltage level on the calculation circuit in a case where the bit width selecting unit selects the first bit width mode, and (ii) impress a voltage of a second voltage level, which is lower than the first voltage level, on the calculation circuit in a case where the bit width selecting unit selects the second bit width mode. 5. The microprocessor of claim 1, further comprising: a clock frequency controlling unit operable to (i) control the operation controlling unit to supply the clock signal of a first frequency to each of the partial calculation circuits, in a case where the bit width selecting unit selects the first bit width mode, and (ii) control the operation controlling unit to supply the clock signal of a second frequency, which is higher than the first frequency, to each of the partial calculation circuits, in a case where the bit width selecting unit selects the second bit width mode; a voltage controlling unit operable to control a voltage level so as to (i) impress a voltage of a first voltage level on the calculation circuit in a case where the bit width selecting unit selects the first bit width mode, and (ii) impress a voltage of a second voltage level, which is lower than the first voltage level, on the calculation circuit in a case where the bit width selecting unit selects the second bit width mode; a control mode selecting unit operable to select a control mode in terms of the frequency of the clock signal to be supplied to each of the partial calculation circuits, and the voltage level of the voltage to be impressed on the calculation circuit; and a switching unit operable to (i) in a case where the control mode selecting unit selects a first control mode, enable the clock frequency controlling unit to control, and disable the voltage controlling unit to control, and (ii) in a case where the control mode selecting unit selects a second control mode, enable the voltage controlling unit to control, and disable the frequency controlling unit to control. 6. The microprocessor of claim 5, further comprising: a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting from when the control mode selecting unit changes from one control mode to another control mode. 7. The microprocessor of claim 1, comprising: a memory access unit operable to access an external memory, wherein if the fetched instruction is an instruction for data-writing into a memory, the execution controlling unit has the memory access unit write one or more pieces of data into the external memory, and the bit width selecting unit selects a bit width mode according to a value stored in a predetermined area of the external memory. 8. The microprocessor of claim 1, wherein: if the fetched instruction is an instruction for data calculation, the bit width selecting unit selects (i) the first bit width mode, in a case where the fetched instruction is an instruction for data calculation on N bits, and (ii) the second bit width mode, in a case where the fetched instruction is an instruction for data calculation on less than N bits. 9. The microprocessor of claim 1, comprising: a data storage unit including an area that stores therein a result of data calculation performed by the calculation circuit, the result being N bits; and a data writing controlling unit operable to (i) in a case where the first bit width mode is selected, have the entire N bits of the result written in the area and (ii) in a case where the second bit width mode is selected, have only a part of the result being less than N bits written in the area. 10. The microprocessor of claim 1, comprising: a data writing controlling unit operable to (i) in a case where the first bit width mode is selected, have the entire N bits of a result outputted from the calculation circuit written in an external memory, and (ii) in a case where the second bit width mode is selected, have only a part of the result being less than N bits written in the external memory. 11. The microprocessor of claim 1, wherein: the calculation circuit includes two partial calculation circuits that each perform partial data calculation on N/2 bits, and the execution controlling unit, if the fetched instruction is an instruction for data calculation on N bits, and also in a case where the bit width selecting unit selects the second bit width mode, (i) have one of the partial calculation circuits perform partial data calculation on lower N/2 bits out of the N bits, before (ii) having the same partial calculation circuit perform partial data calculation on upper N/2 bits, while taking account of an overflow, if any, that has occurred during the partial data calculation on the lower N/2 bits. 12. The microprocessor of claim 1, wherein: the partial calculation circuits each perform partial data calculation upon receiving a number of bits of data supplied, and the operation controlling unit (i) supplies to each of the partial calculation circuits as many number of bits of as possible for that particular partial calculation circuit, in a case where the bit width mode selecting unit selects the first bit width mode, and (ii) suspends the supply of bits of data to a predetermined number of the partial calculation circuits, and supplies to each of the rest of the partial calculation circuits, as many number of bits as possible for that particular partial calculation circuit, in a case where the bit width mode selecting unit selects the second bit width mode. 13. The microprocessor of claim 1, wherein: each of the partial calculation circuits performs data calculation while a predetermined level of a voltage is being impressed thereon, and the operation controlling unit (i) impresses the predetermined level of the voltage on each of all the partial calculation circuits, in a case where the bit width selecting unit selects the first bit width mode, and (ii) suspends the impression of the predetermined level of the voltage on a predetermined number of the partial calculation circuits, and impresses the predetermined level of the voltage on each of the rest of the partial calculation circuits, in a case where the bit width selecting unit selects the second bit width mode. 14. The microprocessor of claim 13, comprising: a memory access unit operable to access an external memory, wherein if the fetched instruction is an instruction for data-writing into a memory, the execution controlling unit has the memory access unit write one or more pieces of data into the external memory, and the bit width selecting unit selects a bit width mode according to a value stored in a predetermined area of the external memory. 15. The microprocessor of claim 13, wherein: if the fetched instruction is an instruction for data calculation, the bit width selecting unit selects (i) the first bit width mode, in a case where the fetched instruction is an instruction for data calculation on N bits, and (ii) the second bit width mode, in a case where the fetched instruction is an instruction for data calculation on less than N bits. 16. A microprocessor that performs processing according to an instruction fetched from a memory, comprising: a calculation circuit that (i) includes partial calculation circuits which each perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation circuits are to perform data calculation, wherein the calculation circuit performs data calculation upon receiving a clock signal; a frequency changing unit operable to change a frequency of the clock signal to be supplied to the calculation circuit; a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting from when the frequency changing unit changes the frequency; a bit width selecting unit operable to select a bit width mode that designates a certain number of bits on which data calculation is to be performed; an execution controlling unit operable to, if the fetched instruction is an instruction for data calculation, control the calculation circuit to perform data calculation; and an operation controlling unit operable to, when the execution controlling unit controls the calculation circuit to perform data calculation, (i) have all the partial calculation circuits operate, in a case where the bit width selecting unit selects a first bit width mode designating N bits, and (ii) suspend operation of a predetermined number of the partial calculation circuits, and have the rest of the partial circulation circuits operate, in a case where the bit width selecting unit selects a second bit width mode designating less than N bits. 17. A microprocessor that performs processing according to an instruction fetched from a memory, comprising: a calculation circuit that (i) includes partial calculation circuits which each perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation circuits are to perform data calculation, wherein the calculation circuit performs data calculation while a predetermined level of a voltage is being impressed thereon; a voltage changing unit operable to change a voltage level to be impressed on the calculation circuit within a predetermined range; a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting when the voltage changing unit changes the voltage level; a bit width selecting unit operable to select a bit width mode that designates a certain number of bits on which data calculation is to be performed; an execution controlling unit operable to, if the fetched instruction is an instruction for data calculation, control the calculation circuit to perform data calculation; and an operation controlling unit operable to, when the execution controlling unit controls the calculation circuit to perform data calculation, (i) have all the partial calculation circuits operate, in a case where the bit width selecting unit selects a first bit width mode designating N bits, and (ii) suspend operation of a predetermined number of the partial calculation circuits, and have the rest of the partial circulation circuits operate, in a case where the bit width selecting unit selects a second bit width mode designating less than N bits. 18. In a microprocessor having a capacity of conserving power and increasing processing speed, the improvement comprising: a data calculation unit including a plurality of partial calculation circuits that can be enabled to perform a calculation process by employing all or less than all of the plurality of partial calculation circuits; a control mode selecting unit for selecting a clock signal frequency from a plurality of frequency levels and a voltage level from a plurality of voltage levels to be applied to those partial calculation circuits enabled to perform the calculation process, wherein an enablement of less than all of the partial calculation circuits saves power consumption at a lower voltage level and/or increases calculation process speed at a higher clock frequency level; a switching unit responsive to the control mode selecting unit to enable a clock frequency control unit to control the plurality of partial calculation circuits in a first control mode and to enable a voltage controlling unit to control the plurality of partial calculation circuits in a second control mode; and a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting from when the control mode selecting unit changes from one control mode to another control mode. 19. The microprocessor of claim 18, further including: a memory access unit operable for accessing an external memory, wherein the control mode selecting unit is enabled by a fetched instruction to operatively enable less than all of the plurality of partial calculation circuits. 20. In a microprocessor having a capacity of conserving power and increasing processing speed, the improvement comprising: a data calculation unit including a plurality of partial calculation circuits that can be enabled to perform a calculation process by employing all or less than all of the plurality of partial calculation circuits; a control mode selecting unit for selecting a clock signal frequency from a plurality of frequency levels and a voltage level from a plurality of voltage levels to be applied to those partial calculation circuits enabled to perform the calculation process, including a bit width selecting unit that changes a bit width mode depending on a number of bits in data to be calculated in a fetched calculation instruction, wherein the control mode selecting unit is enabled by the fetched instruction to operatively enable less than all of the plurality of partial calculation circuits; a switching unit responsive to the control mode selecting unit to enable a clock frequency control unit to control the plurality of partial calculation circuits in a first control mode and to enable a voltage controlling unit to control the plurality of partial calculation circuits in a second control mode; and a memory access unit operable for accessing an external memory to receive data, wherein an enablement of less than all of the partial calculation circuits saves power consumption at a lower voltage level and/or increases calculation process speed at a higher clock frequency level. 21. The microprocessor of claim 20, further comprising: a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting from when the control mode selecting unit changes from one control mode to another control mode. 22. In a microprocessor having a capacity of conserving power and increasing processing speed, the improvement comprising: a data calculation unit including a plurality of partial calculation circuits that can be enabled to perform a calculation process by employing all or less than all of the plurality of partial calculation circuits; a memory access unit operable for accessing an external memory; a control mode selecting unit for selecting a clock signal frequency from a plurality of frequency levels and a voltage level from a plurality of voltage levels to be applied to those partial calculation circuits enabled to perform the calculation process, including a bit width selecting unit for selecting a bit width mode representative of the number of partial calculation circuits to be enabled for a particular calculation process from a value stored in a predetermined area of the external memory, wherein the control mode selecting unit is enabled by a fetched instruction to operatively enable less than all of the plurality of partial calculation circuits; and a switching unit responsive to the control mode selecting unit to enable a clock frequency control unit to control the plurality of partial calculation circuits in a first control mode and to enable a voltage controlling unit to control the plurality of partial calculation circuits in a second control mode; wherein an enablement of less than all of the partial calculation circuits saves power consumption at a lower voltage level and/or increases calculation process speed at a higher clock level frequency level. 23. The microprocessor of claim 22, wherein: the bit width selecting unit selects a first bit width mode when the fetched instruction is an instruction for data calculation of N bits and a second bit width mode when the fetched instruction is an instruction for data calculation on less than N bits. 24. The microprocessor of claim 22, further comprising: a signal stabilizing unit operable to maintain at a predetermined level, for a predetermined period of time, a voltage level of a signal line used for outputting a signal to outside of the microprocessor, the predetermined period starting from when the control mode selecting unit changes from one control mode to another control mode.