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An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit packa

An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

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What is claimed is: 1. A method for forming an electronic packaging assembly, comprising: forming a silicon interposer, wherein the interposer includes micro-machined vias formed through the silicon interposer; attaching a number of flip chips to the silicon interposer, wherein the flip chips coupl

What is claimed is: 1. A method for forming an electronic packaging assembly, comprising: forming a silicon interposer, wherein the interposer includes micro-machined vias formed through the silicon interposer; attaching a number of flip chips to the silicon interposer, wherein the flip chips couple to the micro-machined vias; and coupling a Peltier element to at least one of the flip chips, wherein the Peltier element is physically attached to an insulating layer on a back portion of the flip chip, and has a connection lead electrically connecting one surface of the Peltier element to the back portion of the flip chip, and a second connection lead electrically connecting another surface of the Peltier element to a voltage source. 2. The method of claim 1, wherein attaching a number of flip chips to the silicon interposer includes: coupling a microprocessor chip to the silicon interposer; and coupling a memory chip to the silicon interposer. 3. The method of claim 2, wherein coupling a memory chip to the silicon interposer includes coupling a dynamic random access memory (DRAM) chip to the silicon interposer. 4. The method of claim 2, wherein the method further includes coupling a capacitor to the silicon interposer. 5. The method of claim 1, wherein coupling a Peltier element to at least one of the flip chips includes coupling a Copper (Cu) and p-type semiconductor junction to the flip chip. 6. The method of claim 5, wherein coupling a Copper (Cu) and p-type semiconductor junction to the flip chip includes coupling a p-type semiconductor selected from the group consisting of p-doped Bismuth Telluride (Bi2Te3), p-doped Lead Telluride (PbTe), and p-doped Silicon Germanium (SiGe). 7. The method of claim 1, wherein coupling a Peltier element to at least one of the flip chips includes coupling a Copper (Cu) and n-type semiconductor junction to the flip chip. 8. The method of claim 7, wherein coupling a Copper (Cu) and n-type semiconductor junction to the flip chip includes coupling an n-type semiconductor selected from the group consisting of n-doped Bismuth Telluride (Bi3Te2), n-doped Lead Telluride (PbTe), and n-doped Silicon Germanium (SiGe). 9. A method for packaging an integrated circuit, comprising: providing a silicon interposer having opposing sides; coupling a semiconductor chip to each of the opposing sides of the silicon interposer; coupling the semiconductor chips on each side of the silicon interposer to one another through the silicon interposer by a number of micro-machined vias, wherein the micro-machined vias provide electrical connections between the opposing sides of the silicon interposer; and coupling a Peltier element to at least one of the of the semiconductor chips, wherein the Peltier element is physically attached to an insulating layer on a back portion of the flip chip, and has a connection lead electrically connecting one surface of the Peltier element to the back portion of the flip chip, and a second connection lead electrically connecting another surface of the Peltier element to a voltage source. 10. The method of claim 9, wherein coupling the Peltier element to at least one of the semiconductor chips includes coupling a metal-to-semiconductor Peltier element, wherein the semiconductor includes either an n or p-doped semiconductor alloy formed between Antimony (Sb) and a transition metal (T) from Group VIII, including Cobalt, Rhodium, and Iridium (Co, Rh, and Ir), and wherein the alloy has the general formula Tsb3. 11. The method of claim 9, wherein coupling the Peltier element to at least one of the semiconductor chips includes coupling a metal-to-semiconductor Peltier element, wherein the semiconductor includes either an n or p-doped superlattice comprising alternating layers of (PbTeSe)m and (BiSb)n where m and n are the number of PbTeSe and BiSb monolayers per superlattice period. 12. The method of claim 9, wherein coupling the Peltier element to at least one of the semiconductor chips includes coupling a metal-to-semiconductor Peltier element, wherein the semiconductor is a doped complex oxide. 13. The method of claim 9, wherein coupling the Peltier element to at least one of the semiconductor chips includes coupling a metal-to-semiconductor Peltier element, wherein the semiconductor is selected from the group consisting of n-doped Bismuth Telluride (Bi 2Te3), n-doped Lead Telluride (PbTe), and n-doped Silicon Germanium (SiGe). 14. The method of claim 9, wherein coupling a semiconductor chip to each of the opposing sides of the silicon interposer includes attaching a microprocessor chip to the first side of the silicon interposer. 15. The method of claim 9, wherein coupling a semiconductor chip to each of the opposing sides of the silicon interposer includes attaching a DRAM chip to a second side of the silicon interposer. 16. A method for cooling an integrated circuit, comprising: providing a silicon interposer having opposing sides; coupling a first semiconductor chip to a first side of the silicon interposer; coupling a second semiconductor chip to a second side of the silicon interposer, wherein a number of electrical connections through the silicon interposer couple the first semiconductor chip to the second semiconductor; forming a metal-to-semiconductor junction which couples to an insulator layer on a back portion of the first semiconductor chip on the first side of the silicon interposer, and having at least one connection lead electrically connecting one surface of the Peltier element to the back portion of the flip chip; and passing current through the metal-to-semiconductor junction in a direction such that a Peltier cooling effect occurs adjacent to the first semiconductor chip. 17. The method of claim 16, wherein coupling a first semiconductor chip to the first side of the silicon interposer includes coupling a microprocessor chip to the first side. 18. The method of claim 16, wherein coupling a second semiconductor chip to the second side of the silicon interposer includes coupling a memory chip to the second side of the silicon interposer. 19. The method of claim 16, wherein forming a metal-to-semiconductor junction includes forming a Copper (Cu) and doped Bismuth Telluride (Bi2Te3) junction. 20. The method of claim 19, wherein forming a Copper (Cu) and doped Bismuth Telluride (Bi2Te3) junction includes using vacuum evaporation to form a thin film of p-doped Bismuth Telluride (Bi2Te3). 21. The method of claim 16, wherein forming a metal-to-semiconductor junction includes forming a Copper (Cu) and doped Antimony Telluride (Sb2Te3) junction, wherein forming a Copper (Cu) and doped Antimony Telluride (Sb2Te3) junction includes using vacuum evaporation to form a thin film of doped Antimony Telluride (Sb2Te3). 22. The method of claim 16, wherein forming a metal-to-semiconductor junction includes forming a Copper (Cu) and doped semiconductor junction, wherein the semiconductor is selected from Bismuth Telluride (Bi2Te3), Lead Telluride (PbTe), and Silicon Germanium (SiGe). 23. The method of claim 16, wherein forming a metal-to-semiconductor junction includes forming a metal-to-semiconductor junction which includes a doped superlattice junction, wherein the doped superlattice includes alternating layers of (PbTeSe)m and (BiSb) n where m and n are the number of PbTeSe and BiSb monolayers per superlattice period. 24. The method of claim 16, wherein forming a metal-to-semiconductor junction includes forming a metal-to-semiconductor junction wherein the semiconductor includes a complex oxide semiconductor, and wherein the complex oxide semiconductor includes Strontium (Sr) and Titanium (Ti). 25. A method for heating an integrated circuit, comprising: providing a silicon interposer having opposing sides; coupling a first semiconductor chip to a first side of the silicon interposer; coupling a second semiconductor chip to a second side of the silicon interposer, wherein a number of electrical connections through the silicon interposer couple the first semiconductor chip to the second semiconductor; forming a metal-to-semiconductor junction which couples to an insulator layer on a back portion of the first semiconductor chip on the first side of the silicon interposer, and having at least one connection lead electrically connecting one surface of the Peltier element to the back portion of the flip chip; and passing current through the metal-to-semiconductor junction in a direction such that a Peltier heating effect occurs adjacent to the first semiconductor chip. 26. The method of claim 25, wherein coupling a first semiconductor chip to the first side of the silicon interposer includes coupling a microprocessor chip to the first side. 27. The method of claim 25, wherein coupling a second semiconductor chip to the second side of the silicon interposer includes coupling a memory chip to the second side of the silicon interposer. 28. The method of claim 25, wherein forming a metal-to-semiconductor junction includes forming a metal-to doped semiconductor junction wherein the semiconductor is selected from Bismuth Telluride (Bi2Te3), Lead Telluride (PbTe), and Silicon Germanium (SiGe). 29. The method of claim 25, wherein forming a metal-to-semiconductor junction includes forming a metal and doped superlattice junction, wherein the doped superlattice includes alternating layers of (PbTeSe)m and (BiSb)n where m and n are the number of PbTeSe and BiSb monolayers per superlattice period. 30. The method of claim 25, wherein forming a metal-to-semiconductor junction includes forming a metal and doped complex oxide semiconductor, wherein the complex oxide semiconductor includes Strontium (Sr) and Titanium (Ti).