$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor package with a heat spreader 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/36
  • H01L-023/34
  • H01L-023/12
  • H01L-025/04
출원번호 US-0605163 (2003-09-12)
우선권정보 TW-92104001 A(2003-02-26)
발명자 / 주소
  • Wang,Sung Fei
출원인 / 주소
  • Advanced Semiconductor Engineering, Inc.
대리인 / 주소
    Jianq Chyun IP Office
인용정보 피인용 횟수 : 11  인용 특허 : 19

초록

A semiconductor package with a heat spreader is described, including a first chip, a second chip, a heat spreader and a substrate. The first chip has an active surface over which the second chip is attached. The heat spreader is attached over the first chip. The first chip is bonded onto the substr

대표청구항

The invention claimed is: 1. A multi-chip module (MCM) package, comprising: a substrate having an opening therein; a plurality of first bumps; a first chip that has an active surface bonded to and electrically connected with the substrate through the first bumps, the active surface of the first chi

이 특허에 인용된 특허 (19)

  1. Mittal Faquir C. (Audubon PA), Apparatus for cooling integrated circuit chips with forced coolant jet.
  2. Weber Robert J. (Marion IA), Compact reduced parasitic resonant frequency pulsed power source at microwave frequencies.
  3. Tsung-Ying Hsieh TW; Chin-Lien Hsu TW; Wen-Rui Hsu TW, High power monolithic microwave integrated circuit package.
  4. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
  5. Dudderar Thomas Dixon ; Kossives Dean Paul ; Low Yee Leng, Integrated circuit packages with improved EMI characteristics.
  6. Hashimoto Nobuaki,JPX, Method of mounting a sealed assembly on a mounting substrate and optical transducer.
  7. Hofstee, Harm Peter; Montoye, Robert Kevin; Sprogis, Edmund Juris, Multi-chip integrated circuit module.
  8. Wang, Sung-Fei, Multi-chips package.
  9. Seyama, Kiyotaka; Yamada, Hiroshi; Yamamoto, Haruhiko, Multichip module having chips mounted on upper and under surfaces of a thin film closing an opening formed in a rigid substrate.
  10. Lin, Mou-Shiung; Peng, Bryan, Multiple chips bonded to packaging structure with low noise and multiple selectable functions.
  11. Randy H. Y. Lo TW; Chien-Ping Huang TW; Chi-Chuan Wu TW, Package structure stacking chips on front surface and back surface of substrate.
  12. Yinon Degani ; Thomas Dixon Dudderar ; King Lien Tai, Packaging silicon on silicon multichip modules.
  13. Rife William B., Reverse mount heat sink assembly.
  14. Kosaki, Katsuya; Nakano, Hirofumi; Kunii, Tetsuo, Semiconductor device.
  15. Toshiaki Shinohara JP, Semiconductor package comprising lead frame with punched parts for terminals.
  16. Degani, Yinon; Dudderar, Thomas Dixon; Sun, Liguo; Zhao, Meng, Stacked module package.
  17. Her, Tzong-Dar; Lo, Randy H. Y.; Huang, Chien-Ping, Structure of a multi chip module having stacked chips.
  18. Degani Yinon (Highland Park NJ) Dudderar Thomas Dixon (Chatham NJ) Han Byung Joon (Scotch Plains NJ) Lyons Alan Michael (New Providence NJ), Thin packaging of multi-chip modules with enhanced thermal/power management.
  19. Higuchi Tooru (Kadoma JPX) Yamaguchi Tosiyuki (Kadoma JPX) Kanou Takeshi (Kadoma JPX), Wiring board.

이 특허를 인용한 특허 (11)

  1. Camacho, Zigmund Ramirez; Pisigan, Jairus Legaspi; Advincula, Abelardo Jr. Hadap; Tay, Lionel Chien Hui, Integrated circuit package system with package integration.
  2. Law, Edward; Zhao, Sam Ziqun; Khan, Rezaur Rahman, Low profile ball grid array (BGA) package with exposed die and method of making same.
  3. Pagaila, Reza A., Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die.
  4. Pagaila, Reza A., Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die.
  5. Zhou, Wei; Ma, Zhaohui; Yu, Aibin, Semiconductor die assemblies with heat sink and associated systems and methods.
  6. Zhou, Wei; Ma, Zhaohui; Yu, Aibin, Semiconductor die assemblies with heat sink and associated systems and methods.
  7. Zhou, Wei; Ma, Zhaohui; Yu, Aibin, Semiconductor die assemblies with heat sink and associated systems and methods.
  8. Tsai, Fu-Yung, Semiconductor packages with heat dissipation structures and related methods.
  9. Lin, I-Chia; Tseng, Yu-Chou; Yang, Jin-Feng; Chung, Chi-Sheng; Liao, Kuo-Hsien, Semiconductor packages with thermal dissipation structures and EMI shielding.
  10. Lin, Charles W. C.; Wang, Chia-Chung, Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same.
  11. Lin, Charles W. C.; Wang, Chia-Chung, Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로