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Method of improving copper pad adhesion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/00
  • H01L-023/52
  • H01L-021/44
  • H01L-021/02
출원번호 US-0755282 (2001-01-08)
발명자 / 주소
  • Chen,Sheng Hsiung
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Haynes and Boone, LLP
인용정보 피인용 횟수 : 11  인용 특허 : 53

초록

This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special

대표청구항

The invention claimed is: 1. A bond pad structure, comprising: a semiconductor substrate; a passivating layer forming multiple free-standing vertical islands to provide interlocking grid structures over said semiconductor substrate, wherein the vertical islands are separated by openings in said pas

이 특허에 인용된 특허 (53)

  1. Cheung Robin W. ; Lin Ming-Ren, Advanced copper interconnect system that is compatible with existing IC wire bonding technology.
  2. Chittipeddi Sailesh ; Ryan Vivian, Bond pad design for integrated circuits.
  3. Shiue Ruey-Yun,TWX ; Wu Wen-Teng,TWX ; Shieh Pi-Chen,TWX ; Liu Chin-Kai,TWX, Bond pad structure for the via plug process.
  4. Lin, Shi-Tron; Chan, Chin-Jong, Bond-pad with pad edge strengthening structure.
  5. Hsiao Ming-Shan,TWX, Bonding pad structure and method thereof.
  6. Ming-Tsung Liu (Hsin-Chu TWX) Hsu Bill Y. B. (Chu-Pei TWX) Chung Hsien-Dar (Hu-Wei Town TWX) Wu Der-Yuan (Hsin-Chu TWX), Bonding pad structure and method thereof.
  7. Chan Chin-Jong,TWX ; Chung Hsiu-Hsin,TWX ; Lin Rueyway,TWX, Bonding pad structure for integrated circuit (I).
  8. Yamaha Takahisa,JPX, Bonding pad structure of semiconductor device.
  9. Huang Yung-Sheng,TWX ; Lin Chiu-Ching,TWX ; Lu Chun-Hung,TWX ; Hwang Ruey-Lian,TWX, Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability.
  10. Shih Wei-Yan ; Wilson Arthur ; Subido Willmar, Bonding pads for integrated circuits having copper interconnect metallization.
  11. Buchwalter Leena P. ; Callegari Alessandro Cesare ; Cohen Stephan Alan ; Graham Teresita Ordonez ; Hummel John P. ; Jahnes Christopher V. ; Purushothaman Sampath ; Saenger Katherine Lynn ; Shaw Jane , Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same.
  12. Russell Stephen W. ; Lu Jiong-Ping, Copper bond pad process.
  13. Hong Qi-Zhong (Dallas TX) Jeng Shin-Puu (Plano TX) Havemann Robert H. (Garland TX), Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits.
  14. Hsuan Min-Chih,TWX ; Han Charlie,TWX, Direct contact through hole type wafer structure.
  15. Schnabel Rainer Florian ; Ning Xian J. ; Spuler Bruno, Dual damascene with bond pads.
  16. Mukul Saran ; Charles A. Martin ; Ronald H. Cox, Fine pitch system and method for reinforcing bond pads in semiconductor devices.
  17. Eisele Dieter (Lampertheim DEX) Weimann Klaus (Lampertheim DEX), High-power semiconductor assembly in disk-cell configuration.
  18. Chittipeddi Sailesh ; Cochran William Thomas ; Smooha Yehuda, Integrated circuit with active devices under bond pads.
  19. Clampitt Darwin A., Interconnections for semiconductor circuits.
  20. Kim Hark-moo,KRX ; Jeong Jin-kook,KRX, Interlocked bonding pad structures and methods of fabrication therefor.
  21. Wollesen Donald L., Low capacitance interconnection.
  22. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  23. Ker, Ming-Dou; Jiang, Hsin-Chin, Low-capacitance bonding pad for semiconductor device.
  24. Ming-Dou Ker TW; Hsin-Chin Jiang TW, Low-capacitance bonding pad for semiconductor device.
  25. Narita Kaoru,JPX ; Fujii Takeo,JPX, MOSFET for input/output protective circuit having a multi-layered contact structure with multiple contact holes on a si.
  26. Daubenspeck Timothy Harrison ; Motsiff William Thomas ; Rankin Jed Hickory, Method and structure for a semiconductor fuse.
  27. Teng Kuo-Shi,TWX ; Yung Hao-Chieh,TWX ; Chiang Shing-Shing,TWX ; Lu Wen-Haw,TWX, Method and structure for preventing bonding pads from peeling caused by plug process.
  28. Hugh Li ; Diane J. Hymes, Method for enabling conventional wire bonding to copper-based bond pad features.
  29. Kim Jun K. (Seoul KRX) Lee Kyung I. (Seoul KRX), Method for forming a copper metal wiring with aluminum containing oxidation barrier.
  30. Jeng-Jie Peng TW; Ming-Dou Ker TW; Nien-Ming Wang TW, Method for improving integrated circuits bonding firmness.
  31. Peng, Jeng-Jie; Ker, Ming-Dou; Wang, Nien-Ming, Method for improving integrated circuits bonding firmness.
  32. Fu Wen-Jui,TWX ; Lan Ho-Ku,TWX ; Chao Ying-Chen,TWX, Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation.
  33. Kim Do Heyoung,KRX, Method of fabricating metal line structure.
  34. Ming-Tsung Liu,TWX ; Hsu Bill Y. B.,TWX ; Chung Hsien-Dar,TWX ; Wu Dev-Yuan,TWX, Method of forming a bonding pad.
  35. Shiue Ruey-Yun (Hsin-Chu TWX) Wu Wen-Teng (Hsin-Chu TWX) Shieh Pi-Chen (Hsinchu TWX) Liu Chin-Kai (Hsin-Chu TWX), Method of forming bond pad structure for the via plug process.
  36. Stuart E. Greer, Method of forming copper interconnection utilizing aluminum capping film.
  37. Sheng-Hsiung Chen TW; Fan Keng Yang TW, Method of improving pad metal adhesion.
  38. Galloway Terry R., Removal of extended bond pads using intermetallics.
  39. Edelstein Daniel Charles ; McGahay Vincent ; Nye ; III Henry A. ; Ottey Brian George Reid ; Price William H., Robust interconnect structure.
  40. Bryant Frank R. (Denton TX) Chen Fusen E. (Milpitas CA), Semiconductor bond pad structure and method.
  41. Camilletti Robert Charles (Midland MI) Loboda Mark Jon (Midland MI) Michael Keith Winton (Midland MI), Semiconductor chips suitable for known good die testing.
  42. Fujiki Noriaki,JPX ; Yamashita Takashi,JPX, Semiconductor device and bonding pad structure therefor.
  43. Minakshisundaran Balasubramanian Anand JP, Semiconductor device and method of manufacturing the same.
  44. Anand, Minakshisundaran Balasubramanian, Semiconductor device having a plurality of conductive layers.
  45. Yoshioka Kentaro (Ohiramura JPX), Semiconductor device with anchored interconnection layer.
  46. Langley Rodney C. (Boise ID), Semiconductor device with improved bond pads.
  47. Suwanai Naokatsu,JPX ; Fujioka Yasuhide,JPX, Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method the.
  48. Lopatin Sergey D. ; Iacoponi John A., Semiconductor metalization barrier and manufacturing method therefor.
  49. Ouellet Luc,CAX ; Tremblay Yves,CAX ; Gendron Luc,CAX, Stabilization of the interface between tiN and A1 alloys.
  50. Lien Chuen-Der, Structure for fabricating a bonding pad having improved adhesion to an underlying structure.
  51. Saran Mukul, System and method for bonding over active integrated circuits.
  52. Saran, Mukul; Martin, Charles A., System and method for reinforcing a bond pad.
  53. Anschel Morris (Wappingers Falls NY) Ormond Douglas W. (Wappingers Falls NY) Hayunga Carl P. (Poughkeepsie NY), Thin film metallization process for improved metal to substrate adhesion.

이 특허를 인용한 특허 (11)

  1. Hirano, Koichi; Shiraishi, Tsukasa; Nakatani, Seiichi; Ogawa, Tatsuo, Circuit board, method for manufacturing the same, and semiconductor device.
  2. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  3. Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
  4. Kuo,Yian Liang; Lin,Yu Chang, Integrated circuit package bond pad having plurality of conductive members.
  5. Bohr,Mark T.; Martell,Robert W., Method and apparatus for improved power routing.
  6. Bohr,Mark T.; Martell,Robert W., Method and apparatus for improved power routing.
  7. Fumitake, Mieno, Method for manufacturing twin bit structure cell with silicon nitride layer.
  8. Wood, Alan G.; Ireland, Philip J., Methods of forming through-substrate interconnects.
  9. Wang, Liang; Mohammed, Ilyas; Haba, Belgacem, Micro mechanical anchor for 3D architecture.
  10. Wood, Alan G.; Ireland, Philip J., Semiconductor constructions.
  11. Wood, Alan G.; Ireland, Philip J., Semiconductor constructions having through-substrate interconnects.
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