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Process for automatic dynamic reloading of data flow processors (DFPS) and units with two-or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like) 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-003/00
출원번호 US-0265846 (2002-10-07)
우선권정보 DE-196 54 846(1996-12-27)
발명자 / 주소
  • Vorbach,Martin
  • M체nch,Robert
출원인 / 주소
  • Pact XPP Technologies AG
대리인 / 주소
    Kenyon &
인용정보 피인용 횟수 : 49  인용 특허 : 128

초록

A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory arranged between the functional elements and the higher-level unit; and a control unit configured to move at l

대표청구항

The invention claimed is: 1. A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit, comprising: a configuration memory arranged between the functional elements and the higher-level unit; and a control unit configured to move at least one

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이 특허를 인용한 특허 (49)

  1. Chan, Ian Eu Meng; Tharmalingam, Kumara, Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities.
  2. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
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