Single transistor rare earth manganite ferroelectric nonvolatile memory cell
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-029/792
H01L-029/66
출원번호
US-0362387
(2001-08-24)
국제출원번호
PCT/US02/013095
(2001-08-24)
§371/§102 date
20030221
(20030221)
국제공개번호
WO02/082510
(2002-10-17)
발명자
/ 주소
Gnadinger,Fred P.
출원인 / 주소
COVA Technologies, Inc.
대리인 / 주소
Hogan &
인용정보
피인용 횟수 :
17인용 특허 :
98
초록▼
A memory device is formed of the one transistor cell type. Such a device has a substrate, a ferroelectric layer which is a film of rare earth manganite, and an interfacial oxide layer being positioned between the substrate and the ferroelectric layer. The invention includes such a device and method
A memory device is formed of the one transistor cell type. Such a device has a substrate, a ferroelectric layer which is a film of rare earth manganite, and an interfacial oxide layer being positioned between the substrate and the ferroelectric layer. The invention includes such a device and methods of making the same.
대표청구항▼
What is claimed is: 1. A memory device comprising: a substrate; a ferroelectric layer, said layer being a film of rare earth manganite; and an interfacial oxide layer being positioned between the substrate and the ferroelectric layer, wherein the ferroelectric layer has the general formula A 3+MnO
What is claimed is: 1. A memory device comprising: a substrate; a ferroelectric layer, said layer being a film of rare earth manganite; and an interfacial oxide layer being positioned between the substrate and the ferroelectric layer, wherein the ferroelectric layer has the general formula A 3+MnOx in which A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu and x is between 1 and 3 inclusive. 2. The memory device of claim 1 further comprising a Pt gate electrode. 3. The memory device of claim 1 further comprising an Ir, IrO2, RuOx, Ro, RoOx, or indium tin oxide (ITO) gate electrode. 4. The memory device of claim 1 further comprising a doped polycrystalline silicon gate electrode. 5. The memory device of claim 1 further comprising a polycide gate electrode. 6. The memory device of claim 1 further comprising a source region and a drain region. 7. The memory device of claim 1 wherein the interfacial layer comprises silicon, oxygen and at least one of the elements of the rare earth manganite film in the formula SixOy,Az where A is being selected from the group A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu and x is between 0 and 2, y is between 1 and 3, and z is between 0 and all inclusive. 8. The memory device of claim 1 wherein the rare earth manganite film comprises a rare earth manganite film having a relative dielectric permittivity of less than 30. 9. The memory device of claim 1 further comprising a standard, non ferroelectric CMOS transistor in connection with the substrate and encapsulated with a protective layer to prevent contamination from the rare earth elements and the manganese coming from the ferroelectric layer and the interfacial oxide layer.
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