초록 ▼

A receive filter receives signals from a communication channel. The received signals correspond to original Walsh covered chip sequences transmitted by a transmit filter through the communication channel to the receive filter. The received signals are processed by an equalizer to generate a soft est

A receive filter receives signals from a communication channel. The received signals correspond to original Walsh covered chip sequences transmitted by a transmit filter through the communication channel to the receive filter. The received signals are processed by an equalizer to generate a soft estimate of chip sequences corresponding to the original Walsh covered chip sequences. An N chip Walsh decover is then utilized to generate a soft estimate of code symbols corresponding to the soft estimate of the chip sequences. A number of symbol slicers are then used in parallel to produce a hard estimate of the code symbols corresponding to the soft estimate of code symbols generated by the N chip Walsh decover. Thereafter an N chip Walsh cover is used as part of a scheme to generate a hard estimate of chip sequences corresponding to the hard estimate of the code symbols generated by the symbol slicers. The hard estimate of the chip sequences generated with the aid of the N chip Walsh cover, and the soft estimate of the chip sequences generated by the equalizer, are used to generate a tracking mode error signal to adapt the response of the equalizer to the received signals.

대표청구항 ▼

What is claimed is: 1. A method for a spread spectrum communication system, comprising: generating a soft estimate of a sequence of chips, for decoding a received channel in said spread spectrum communication system; Walsh decovering said soft estimate of said sequence of chips to produce a soft e

What is claimed is: 1. A method for a spread spectrum communication system, comprising: generating a soft estimate of a sequence of chips, for decoding a received channel in said spread spectrum communication system; Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips; comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; applying said error signal to adapt a response of an equalizer used for said generating said soft estimates of said sequence of chips. 2. The method of claim 1 further comprising: transmitting a signal carrying said sequence of chips of said channel to said equalizer for said generating said soft estimates of said sequence of chips. 3. The method of claim 1 further comprising: adapting a tap weight of a multiplier of said equalizer for said applying said error signal. 4. An apparatus for a spread spectrum communication system, comprising: means for generating a soft estimate of a sequence of chips, for decoding a received channel in said spread spectrum communication system; means for Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; means for applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; means for Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips; means for comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; means for applying said error signal to adapt a response of an equalizer used for said generating said soft estimates of said sequence of chips. 5. The apparatus of claim 4 further comprising: means for transmitting a signal carrying said sequence of chips of said channel to said equalizer for said generating said soft estimates of said sequence of chips. 6. The apparatus of claim 3 further comprising: means for adapting a tap weight of a multiplier of said equalizer for said applying said error signal. 7. A method for a spread spectrum communication system, comprising: transmitting a signal carrying a sequence of chips of a communication channel; receiving said signal at a receiver in said spread spectrum communication system; processing said signal for generating a soft estimates of said sequence of chips for an equalizer; Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips; comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; applying said error signal to adapt a response of said equalizer for said generating said soft estimates of said sequence of chips while adapting a tap weight of a multiplier of said equalizer by said applying said error signal. 8. An apparatus for a spread spectrum communication system, comprising: means for transmitting a signal carrying a sequence of chips of a communication channel; means for receiving said signal at a receiver in said spread spectrum communication system; means for processing said signal for generating a soft estimates of said sequence of chips for an equalizer; means for Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; means for applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; means for Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips; means for comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; means for applying said error signal to adapt a response of said equalizer for said generating said soft estimates of said sequence of chips while adapting a tap weight of a multiplier of said equalizer by said applying said error signal. 9. A method for operation of an equalizer, comprising: generating a soft estimate of a sequence of chips; Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips. 10. The method as recited in claim 9 further comprising: comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; applying said error signal to adapt a response of said equalizer used for said generating said soft estimates of said sequence of chips. 11. The method of claim 10 further comprising: adapting a tap weight of a multiplier of said equalizer for said applying said error signal. 12. An apparatus for operation of an equalizer, comprising: means for generating a soft estimate of a sequence of chips; means for Walsh decovering said soft estimate of said sequence of chips to produce a soft estimate of a plurality of symbols; means for applying a slicing operation to said soft estimate of said plurality of symbols to generate a hard estimate of said plurality of symbols; Walsh covering said hard estimate of said plurality of symbols to produce a hard estimate of said sequence of chips. 13. The apparatus as recited in claim 12 further comprising: means for comparing said soft estimate of said sequence of chips with said hard estimate of said sequence of chips to generate an error signal; means for applying said error signal to adapt a response of said equalizer used for said generating said soft estimates of said sequence of chips. 14. The apparatus of claim 12 further comprising: means for adapting a tap weight of a multiplier of said equalizer for said applying said error signal.