A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch.
A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
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What is claimed is: 1. A method of fabricating a semiconductor device, comprising: providing a layer of high-k dielectric material over a substrate; providing a layer of conductive material over the high-k dielectric layer; patterning the conductive layer; providing spacers along sidewalls of th
What is claimed is: 1. A method of fabricating a semiconductor device, comprising: providing a layer of high-k dielectric material over a substrate; providing a layer of conductive material over the high-k dielectric layer; patterning the conductive layer; providing spacers along sidewalls of the patterned conductive layer; performing a first etch on the high-k dielectric layer, wherein a portion of the high-k dielectric layer being etched with the first etch remains after the first etch; and performing a second etch of the high-k dielectric layer to remove at least part of the remaining portion of the high-k dielectric layer, wherein the second etch differs from the first etch, wherein the first and second etches of the high-k dielectric layer are performed, at least in part, in alignment with the spacers. 2. The method of claim 1, wherein the first etch is a dry etch process. 3. The method of claim 2, wherein the dry etch process is a reactive ion etching process using an etch chemistry comprising at least one of inert gas, chlorine, and fluorine. 4. The method of claim 1, wherein the second etch is a wet etch process. 5. The method of claim 4, wherein the wet etch process uses an etch chemistry comprising an inorganic acid. 6. The method of claim 5, wherein the inorganic acid comprises at least one of a halogen acid, HF, and H2SO. 7. A method of fabricating a semiconductor device, comprising: providing a layer of high-k dielectric material over a substrate; providing a layer of conductive material over the high-k dielectric layer; patterning the conductive layer; performing a first etch on the high-k dielectric layer, wherein a portion of the high-k dielectric layer being etched with the first etch remains after the first etch; and performing a second etch of the high-k dielectric layer to remove at least part of the remaining portion of the high-k dielectric layer, wherein the second etch differs from the first etch, wherein the patterning of the conductive layer, the first etch, and the second etch are performed in a same chamber. 8. The method of claim 1, wherein the high-k dielectric material comprises at least one of an aluminum oxide, a zirconium oxide, a hafnium oxide, a hafnium silicate, a zirconium silicate, a silicon nitride, a tantalum oxide, a barium strontium titanate, and a lead-lanthanum-zirconium-titanate. 9. A method of fabricating a semiconductor device, comprising: providing a layer of high-k dielectric material over a substrate; providing a layer of conductive material over the high-k dielectric layer; patterning the conductive layer; performing a first etch on the high-k dielectric layer, wherein a portion of the high-k dielectric layer being etched with the first etch remains after the first etch; changing material properties of the remaining portion of the high-k dielectric layer during the first etch; and performing a second etch of the high-k dielectric layer to remove at least part of the remaining portion of the high-k dielectric layer, wherein the second etch differs from the first etch. 10. The method of claim 1, wherein the high-k dielectric layer is provided using a process selected from a group consisting of chemical vapor deposition, metal-organic chemical vapor deposition, atomic layer deposition, atomic layer chemical vapor deposition, low pressure chemical vapor deposition, sputtering, and anodization. 11. The method of claim 1, wherein the high-k dielectric layer has an initial thickness prior to the tint etch, wherein the remaining portion of the high-k dielectric layer has a first thickness after the first etch, the first thickness being about half the initial thickness. 12. The method of claim 7, wherein the first and second etches of the high-k dielectric layer are performed in alignment with the patterned conductive layer. 13. The method of claim 7, wherein the first etch is a dry etch process. 14. The method of claim 7, wherein the second etch is a wet etch process. 15. The method of claim 7, further comprising: changing material properties of the remaining portion of the high-k dielectric layer during the first etch. 16. The method of claim 9, wherein the first and second etches of the high-k dielectric layer are preformed in alignment with the patterned conductive layer. 17. The method of claim 9, wherein the first etch is a dry etch process. 18. The method of claim 9, wherein the second etch is a wet etch process. 19. The method of claim 9, wherein the patterning of the conductive layer, the first etch, and the second etch are performed in a same chamber.
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