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A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of

A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

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What is claimed is: 1. In a system comprising two identical but independently operated parallel path closed rings of successively corrected and respectively clocked sequential data address generators, wherein a source of a stream of successively clocked data packets each provided with headers inclu

What is claimed is: 1. In a system comprising two identical but independently operated parallel path closed rings of successively corrected and respectively clocked sequential data address generators, wherein a source of a stream of successively clocked data packets each provided with headers including error detection code facility flows along a first such path, a method of correcting data error in a packet and substituting therefor a correct data packet without interrupting the flow of the stream of data packets along said first path, that comprises, simultaneously flowing from said source a second identical stream of the successive data packets along a separate parallel second path; synchronizing the operation of said first and second data packet flow paths; at intervals along the separate data packet flows, convergingly linking the first and second flow paths at a common point of each of the respective rings and comparing the corresponding data packets from each flow path at such link point; in the event that one of the compared data packets of one of the flow paths has been determined by its error detection code to be an error, discarding such erroneous data packet and using the corresponding data packet of the other flow path in substitution therefore; and re-synchronizing the operation of the first and second data packet flow paths to continue an uninterrupted stream of data packet flow following such convergence. 2. The method of claim 1 wherein while the data packets may be clocked at the same frequency or at different frequencies along the first and second paths, the data flow therealong is at different speeds. 3. The method of claim 2 wherein the clocking frequencies are substantially the same and said different speeds are only slightly different. 4. The method of claim 1 wherein, the data packet of that path that arrives first at the convergence link point of the rings is stored until the arrival of the corresponding data packet of the other path; and then, if one of the data packets is an error, the correct data packet of the other path is released to continue the data packet flow; but if both data packets are correctly the same, they are both released in momentary synchronized release of stream flows along both separate paths. 5. The method of claim 1 wherein each data stream flow path comprises a cyclical routing of successive data information packets along a closed ring. 6. The method of claim 5 wherein said data packet information comprises address messages generated by successive address generators connected in the ring and receiving address requests from data stream line cards. 7. The method of claim 6 wherein said line cards are fed from a shared memory output-buffered switch fabric. 8. In an address generating system for receiving address requests for a stream of data packet headers received by a traffic manager, the method of generating a corresponding stream of address data, that comprises, providing two identical but independently operated closed rings of successively connected and clocked address generators; synchronizing the operation of both address generator rings; applying the same received stream of data packet headers from the traffic manager to each of the address generator rings successively to generate requests for identical address data along each address generator ring and to return to the traffic manager identical address responses; linking the rings at a common convergence point at an end of each ring such that when address data arrives from an address generator at such end of the ring, it is stored to await the corresponding address data from the corresponding address generator of the other ring for comparison at said ring end point; in the event that such address data from one of the rings is in error and thus different from the corresponding correct address data from the other ring, discarding the erroneous address data and inserting the correct address data from the other ring in its place; and re-synchronizing the operation of both rings to enable continual real-time flow of the stream of address data from said ring end point corrected to substitute the correct address data for the erroneous address data. 9. The method of claim 8 wherein the determination of the erroneous data is made through error detection code in said header. 10. The method of claim 8 wherein said synchronizing compensates for both address generator clocking frequency differences and timing skew, and for traffic manager address request a synchronism. 11. A fault-tolerance method for protecting against and for correcting errors in packet data stream flow, that comprises applying the same packet data stream to each of a pair of independent parallel data flow path, each containing independently operated parallel closed rings of successively connected and respectively clocked sequential data address generators; initially synchronizing the flow in the paths; linking the paths at predetermined intervals at a common convergence point of the rings and comparing the corresponding data in each path at such ring linking points in order to detect a possible error in the data occurring in one of the paths; substituting for such data error in one of the paths the corresponding correct data from the other path; and re-synchronizing the flow in the paths to enable continuation of the data stream flow without interruption and without error. 12. The method of claim 11 wherein each path comprises an identical closed ring of sequential packet data address generators. 13. The method of claim 12 wherein said predetermined intervals are located at the ends of the closed rings. 14. An address generating system for receiving address requests for a stream of data packet headers received by a traffic manager, having, in combination, two identical but independently operated parallel closed rings of successively connected and respectively clocked sequential address generators; means for synchronizing the operation of both sequential address generator rings; traffic manager for applying the same stream of data packet headers to each of the address generator rings successively to generate requests for identical address data along each address generator ring and to return to the traffic manager identical address responses; means for linking ends of the rings at a common convergence point such that when address data arrives from an address generator at an end of the ring, it is stored to await the corresponding address data from the corresponding address generator of the other ring for comparison at said point; in the event that such address data from one of the rings is in error and thus different from the corresponding correct address data from the other ring, means discarding the erroneous address data and inserting the correct address data from the other ring in its place at said point; and means for re-synchronizing the operation of both rings to enable continual real-time flow of the stream of address data corrected to substitute the correct address data for the erroneous address data. 15. The system of claim 14 wherein an error detection code facility is provided in said header for making a determination of the erroneous data. 16. The system of claim 14 wherein the synchronizing means compensates for both address generator clocking frequency differences and timing skew, and for traffic manager address request a synchronism. 17. The system of claim 14 wherein said address request are from data stream line cards fed from a shared memory output-buffered switch fabric. 18. The system of claim 14 wherein the address generator ring synchronizing means enables each ring to be presented with an identical view of memory allocation to the extent that, for the same data packet, each ring assigns the same address in memory. 19. The system of claim 18 wherein means is provided for address request synchronizing of the traffic manager to each address generator ring to insure that each data packet is accepted by each ring in the same packet frame. 20. The system of claim 19 wherein said synchronizing is achieved both as to the two address generator rings and as to each traffic manager to both address generator rings, whereby both address generator rings produce the same data address for the same data packet. 21. The system of claim 14 wherein the address data storing is effected with FIFO units associated with the address generators. 22. The system of claim 14 wherein the traffic manager is adjusted to send an address request every 32 nS with the traffic manager and address generators being clocked at 8 nS periods on average, such that each traffic manager sends one address request in an input period of every four clock cycles. 23. The system of claim 22 wherein the traffic manager is adjusted to send an address request at the first clock cycle of every four-clock cycle input period. 24. The system of claim 23 wherein an address generator receiving such an address request receives the same in the first two cycles of said input period and is adjusted to process the requests during the next input period, allowing two cycles of time buffering or de-skewing. 25. The system of claim 23 wherein four traffic managers are provided for synchronization to an address generator on a ring, each provided with a 2-bit counter clocked at 8 nS, with the traffic manager sending an address request to each address generator when said counter is at zero and stalling any request until the counter is at zero. 26. The system of claim 25 wherein each address generator maintains a 2-bit de-skew counter for each traffic manager. 27. In a system comprising two identical but independently operated parallel path rings of successively connected and respectively clocked sequential data address generators, wherein a source of a stream of successively clocked data packets each provided with headers including error detection code facility flows along a first such path, apparatus for correcting data error in a packet and substituting therefor a correct data packet without interrupting the flow of the stream of data packets along said first path, having, in combination, means for simultaneously flowing from said source a second identical stream of the successive data packets along a separate parallel second path; means for synchronizing the operation of said first and second data packet flow paths; means located at intervals along the separate data packet flows, convergingly linking at a common point of each of said rings the first and second flow paths and comparing the corresponding data packets from each flow path at such link point; in the event that one of the compared data packets of one of the flow paths has been determined by its error detection code to be an error, means for discarding such erroneous data packet and using the corresponding data packet of the other flow path in substitution therefore; and means for re-synchronizing the operation of the first and second data packet flow paths to continue an uninterrupted stream of data packet flow following such convergence at said point. 28. The apparatus of claim 27 wherein the data packets are clocked at the same frequency or at different frequencies along the first and second paths, while the data flow therealong is at different speeds. 29. The apparatus of claim 28 wherein the clocking frequencies are substantially the same and said different speeds are only slightly different. 30. The apparatus of claim 27 wherein storage means is provided for storing the data packet of that path that arrives first at the convergence link point until the arrival of the corresponding data packet of the other path; and then, if one of the data packets is an error, means is provided or enabling the corresponding correct data packet of the other path to be released to continue the data packet flow; but if both data packets are correctly the same; they are both released in momentary synchronized release along both separate paths.