초록 ▼

In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using mu

In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing paths may be established using multiple components or may share components. When the processing paths share components, only one of the processing paths may be used at a time.

대표청구항 ▼

What is claimed is: 1. A system comprising: a bus; and a digital signal processor comprising: a first multiplexer and a second multiplexer operative to receive a plurality of n-bit data sets from the bus and to select a single n-bit data set from the plurality of n-bit data sets to be processed; a

What is claimed is: 1. A system comprising: a bus; and a digital signal processor comprising: a first multiplexer and a second multiplexer operative to receive a plurality of n-bit data sets from the bus and to select a single n-bit data set from the plurality of n-bit data sets to be processed; a multiplier having a first structure and a second structure, the first structure processing data up to n-bits and the second structure processing data up to (n/2)-bits; and a data size selector which configures the multiplier into the first structure of a single n-bit multiplier when the selected data set is greater than (n/2)-bits and configures the multiplier into the second structure of two (n/2)-bit multipliers when the selected data set is (n/2)-bits or less. 2. The system of claim 1, further comprising a plurality of arithmetic logic units to collect the processed data set through a plurality of multiplexers. 3. The system of claim 1, further comprising a flop which stores the result of the multiplier. 4. The system of claim 3, further comprising at least one arithmetic logic unit which adds the result from the multiplier to a running total. 5. A method comprising: selecting a single n-bit data set from a plurality of data sets; determining a size of the selected data set to be processed; configuring a first processing path for data set of n-bits if the selected data set size is greater than (n/m)-bits; and dividing the first processing path into multiple processing paths if the selected data set size is (n/m)-bits or less. 6. The method of claim 5, further comprising configuring each of the multiple processing paths for data set sizes smaller than the first processing path. 7. The method of claim 5, further comprising dividing the first processing path into m processing paths. 8. The method of claim 5, further comprising including an n-bit multiplier in the first processing path. 9. The method of claim 5, further comprising defining m=2.