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Internal firewall for a personal computer to deny access by a network to a user's secure portion 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/173
  • G06F-015/16
출원번호 US-0669730 (2000-09-26)
발명자 / 주소
  • Ellis,Frampton E.
출원인 / 주소
  • Ellis,Frampton E.
대리인 / 주소
    DLA Piper Rudnick Gray Cary US LLP
인용정보 피인용 횟수 : 29  인용 특허 : 30

초록

A system and method is provided for an internal firewall configured to operate in a personal computer, which is configured to operate with other computers connected to a network. The personal computer includes at least two microprocessors. The firewall is configured to deny access to a first micropr

대표청구항

The invention claimed is: 1. An apparatus, comprising: a firewall configured to operate in a personal computer, which is configured to operate with other computers connected in a network; said personal computer including at least two microprocessors; said firewall configured to deny access to at l

이 특허에 인용된 특허 (30)

  1. Tuck David ; Weier Bruce ; Stojka John, Apparatus and method for trading electric energy.
  2. Chung Pi-Yu ; Fowler Glenn Stephen ; Huang Yennun ; Vo Kiem-Phong ; Wang Yi-Min, Apparatus and methods for sharing idle workstations.
  3. Lee Wayman ; Miller Wayne H. ; Helm Bradley C., Appliance having EMI shielding.
  4. Butts ; Jr. H. Bruce (Redmond WA) Leahy James N. (Boston MA) Gillett ; Jr. Richard B. (Westford MA), Bus event monitor.
  5. Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
  6. Govett Ian Robert, Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/con.
  7. Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
  8. Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
  9. Orimo Masayuki (Kawasaki JPX) Mori Kinji (Yokohama JPX) Suzuki Yasuo (Ebina JPX) Kawano Katsumi (Kawasaki JPX) Takeuchi Masuyuki (Fujisawa JPX) Matsuura Masayoshi (Hitachi JPX) Teranishi Yuko (Kogane, Control method for distributed processing system.
  10. Hodroff Joel (Minneapolis MN), Currency and barter exchange debit card and system.
  11. Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
  12. Coley Christopher D. ; Wesinger ; Jr. Ralph E., Firewall system for protecting network elements connected to a public network.
  13. Hagersten Erik E. ; Hill Mark D., Hierarchical SMP computer system.
  14. Robertazzi Thomas G. ; Luryi Serge ; Sohn Jeeho, Load sharing controller for optimizing monetary cost.
  15. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
  16. Hornbuckle Gary D. (Pebble Beach CA), Method and apparatus for remotely controlling and monitoring the use of computer software.
  17. Belville Daniel R. ; Goble George R., Method and system for allowing remote procedure calls through a network firewall.
  18. Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Melvin James (Bolton MA), Method of handling errors in software.
  19. Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
  20. Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
  21. Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
  22. Crosetto Dario B. (DeSoto TX), Parallel processing data network of master and slave transputers controlled by a serial control network.
  23. Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
  24. Gelb Edward J. (Wayne NJ), Security system for preventing unauthorized communications between networks by translating communications received in ip.
  25. Kobata Hiroshi, Smart internet information delivery system having a server automatically detects and schedules data transmission based o.
  26. Shi Yuan (Wayne PA), System for automatically generating efficient application - customized client/server operating environment for heterogen.
  27. Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
  28. Trugman Rodney M. (Roswell GA), Systems and methods for work assignment and distribution from a server to remote/mobile nodes.
  29. Comroe Richard A. (Dundee IL) Furtaw Robert W. (Lake Zurich IL), TDM hand-off technique using time differences.
  30. Judson David H. (6823 Northport Dallas TX 75230), Web browser with dynamic display of information objects during linking.

이 특허를 인용한 특허 (29)

  1. Ellis, Frampton E., Computer or microchip controlled by a firewall-protected master controlling microprocessor and firmware.
  2. Ellis, Frampton E., Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller.
  3. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
  4. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
  5. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
  6. Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.
  7. Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.
  8. Ellis, Frampton E., Computer or microchip with a secure system bios having a separate private network connection to a separate private network.
  9. Ellis, Frampton E., Computer or microchip with an internal hardware firewall and a master controlling device.
  10. Ellis, Frampton E., Computer or microchip with its system bios protected by one or more internal hardware firewalls.
  11. Ellis, Frampton E., Computer with at least one faraday cage and internal flexibility sipes.
  12. Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
  13. Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.
  14. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewalls.
  15. Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
  16. Ellis, Frampton E., Computers including an undiced semiconductor wafer with Faraday Cages and internal flexibility sipes.
  17. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.
  18. Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.
  19. Ellis, Frampton E., Footwear sole sections including bladders with internal flexibility sipes therebetween and an attachment between sipe surfaces.
  20. Fuh,Tzong Fen; Fan,Serene H.; Qu,Diheng, Local authentication of a client at a network device.
  21. Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
  22. Ellis, Frampton E., Method of using one or more secure private networks to actively configure the hardware of a computer or microchip.
  23. Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
  24. Ellis, Frampton E., Microchip with faraday cages and internal flexibility sipes.
  25. Ellis, Frampton E, Microchips with an internal hardware firewall.
  26. Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.
  27. Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.
  28. Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.
  29. Ellis, Frampton E., Surgically implantable device enclosed in two bladders configured to slide relative to each other and including a faraday cage.
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