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A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The waf

A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

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What is claimed is: 1. A method of forming a semiconductor device comprising: implanting ions through a first surface of a monocrystalline semiconductor material to a selected depth forming an amorphous layer adjacent the first surface; heating the semiconductor material under conditions effective

What is claimed is: 1. A method of forming a semiconductor device comprising: implanting ions through a first surface of a monocrystalline semiconductor material to a selected depth forming an amorphous layer adjacent the first surface; heating the semiconductor material under conditions effective to coalesce a substantially planer zone formed by the implantation of ions through the first surface of the semiconductor material to form a gettering zone and further to convert the amorphous layer to a first layer of semiconductor material forming an insulating bond layer on a surface of the handle wafer; and bonding the insulating bond layer to the first surface of the semiconductor material. 2. The method of claim 1, wherein implanting ions through a first surface of the monocrystalline semiconductor material to a selected depth further comprises: implanting ions of the semiconductor material. 3. The method of claim 1, wherein implanting ions through a first surface of the monocrystalline semiconductor material to a selected depth further comprises: implanting silicon ions. 4. The method of claim 1, further comprising: forming devices in a second layer of semiconductor material to form an integrated circuit, wherein the second layer of semiconductor material has not been exposed to ion implantation. 5. The method of claim 1, further comprising: forming at least one device in a second layer of semiconductor material, wherein the second layer of semiconductor material has not been exposed to ion implantation. 6. The method of claim 5, wherein the at least one device is a device from a group of devices consisting of a bipolar junction transistor, a field effect transistor, a capacitor, a resistor and a thyristor. 7. The a method of forming an integrated circuit in a wafer of semiconductor material, the method comprising: implanting ions through a first surface of the wafer to form a first amorphous layer adjacent the first surface of the wafer; annealing the wafer to convert the first amorphous layer to a first monocrystalline semiconductor layer; bonding a handle wafer to the first surface of the wafer; and forming semiconductor devices in a second layer of the wafer adjacent a second surface of the wafer, wherein the second layer has not been exposed to the ion implantation. 8. The method of claim 7, wherein annealing the wafer to convert the first surface of the wafer comprises: heating the wafer from 450째 C. to 1200째 for about 15 minutes to 8 hours. 9. The method of claim 7, wherein implanting the ions to form the first amorphous layer further comprises: implanting ions of the semiconductor material of the wafer to form the first amorphous layer. 10. The method of claim 7, wherein bonding the handle wafer to the first surface of the wafer, further comprises: forming an insulating bond layer on a surface of the handle wafer; and bonding the insulating bond layer to the first surface of the wafer. 11. The method of claim 7, further comprising: thinning the second layer of the wafer to a desired thickness. 12. The method of claim 11, wherein the method of thinning the second layer of the wafer to the desired thickness is a method from a group of methods consisting of etching, lapping, grinding and polishing. 13. The method of claim 7, wherein implanting the ions to form the first amorphous layer further comprises: forming a oxide layer overlaying the first surface of the wafer; and implanting the ions through the oxide layer. 14. The method of claim 13, further comprising: removing the oxide layer after the implantation of ions. 15. The method of claim 7, further comprising: forming a gettering zone between the first monocrystalline semiconductor layer and the second layer of the wafer. 16. The method of claim 15, wherein forming the gettering zone further comprises: heating the wafer from 800째 C. to 1200째 for about 1 to 6 hours. 17. A method of forming an integrated circuit in a monocrystalline semiconductor wafer, the method comprising: implanting ions through a first surface of the wafer to form a first layer of amorphous material adjacent the first surface of the wafer which extends a select depth from the first surface; annealing the first layer of amorphous layer to form a first monocrystalline semiconductor layer; forming a gettering zone containing active gettering sites between the first layer monocrystalline semiconductor material and a second layer of monocrystalline material, wherein the second layer of monocrystalline material has not been exposed to ion implementation; bonding a handle wafer to the first surface of the wafer; and forming devices in the second layer of monocrystalline material to form the integrated circuit. 18. The method of claim 17, wherein implanting the ions to form the first layer of amorphous material a select depth further comprises: controlling the energy used to implant the ions.