초록 ▼

A system and method for increasing speed and efficiency of data buffers is described. A complement reset buffer is provided comprising two pulse generators and an output stage. The first generator responds to a rising edge in a data signal and the second generator responds to a falling edge in a dat

A system and method for increasing speed and efficiency of data buffers is described. A complement reset buffer is provided comprising two pulse generators and an output stage. The first generator responds to a rising edge in a data signal and the second generator responds to a falling edge in a data signal. Each generator is disabled by looping its output back to its input. A reset is also provided for each generator to re-enable the generator during a complement transition in the data signal. A method describing the optimization of the buffer is also described.

대표청구항 ▼

What is claimed is: 1. A buffer circuit for receiving an input signal and for providing an output signal, the buffer comprising: a first pulse generator coupled to receive the input signal and configured to generate a first pulse responsive to a first transition edge of the input signal; a first pu

What is claimed is: 1. A buffer circuit for receiving an input signal and for providing an output signal, the buffer comprising: a first pulse generator coupled to receive the input signal and configured to generate a first pulse responsive to a first transition edge of the input signal; a first pulse loop generator coupled to receive the first pulse from the first pulse generator and configured to generate a first pulse loop signal to deactivate the first pulse generator responsive to the first pulse; a second pulse generator coupled to receive the input signal and configured to generate a second pulse responsive to a second transition edge of the input signal; a second pulse loop generator coupled to receive the second pulse from the second pulse generator and configured to generate a second pulse loop signal to deactivate the second pulse generator responsive to the second pulse; an output stage coupled to receive the first and second pulses and configured to produce an output of first logic value for the duration of the first pulse, and of second logic value for the duration of the second pulse as the output signal from the buffer circuit; a first loop keeper circuit coupled to intercept the first pulse loop signal between the first pulse loop generator and the first pulse generator and configured to deactivate the first pulse generator responsive to receiving the first pulse loop signal, thereby blocking subsequent first pulse loop signals from reaching the first pulse generator; a reset generator coupled to receive the input signal and to output a first reset signal responsive to a falling edge of the input signal; and a first pulse reset coupled to receive the first reset signal from the reset generator and responsive to the first reset signal configured to deactivate the first loop keeper circuit and to reset the first pulse generator to respond to a subsequent rising edge in the input signal. 2. The buffer circuit of claim 1, wherein the buffer receives the input signal from a first a data distribution circuit and provides the output signal to a second data distribution circuit. 3. The buffer circuit of claim 1, further comprising: a second loop keeper circuit coupled to receive the second pulse loop signal from second pulse loop generator and configured to deactivate the second pulse generator responsive to receiving the second pulse loop signal, thereby blocking subsequent second pulse loop signals from reaching the second pulse generator; the reset generator coupled to receive the input signal and to output a second reset signal responsive to a rising edge of the input signal; and a second pulse reset coupled to receive the second reset signal from the reset generator and responsive to the second reset signal, configured to deactivate the second loop keeper circuit and to reset the second pulse generator to respond to a subsequent falling edge in the input signal. 4. The buffer circuit of claim 1, wherein the output stage comprises a keeper circuit configured to hold the output signal constant between first and second pulses. 5. The buffer circuit of claim 1, wherein the first and second pulse generators and the output stage are configured to be large devices. 6. The buffer circuit of claim 1, wherein the width of the first pulse is determined by the amount of delay between the first pulse generator producing the first pulse and the first pulse loop generator producing the first pulse loop signal. 7. The buffer circuit of claim 1, wherein the width of the second pulse is determined by the amount of delay between the second pulse generator producing the second pulse and the second pulse loop generator producing the second pulse loop signal. 8. The buffer circuit of claim 1, wherein the first and second pulse generators are configured to receive a level signal from the input signal, and the output stage is configured to generate a level signal as the output signal. 9. The buffer circuit of claim 1, wherein: the input signal comprises a positive pulse input and a negative pulse input; the first pulse generator is configured to receive the positive pulse input; the second pulse generator is configured to receive the negative pulse input; and the output stage is configured to generate a level signal as the output signal. 10. The buffer circuit of claim 1, wherein: the input signal comprises a positive pulse input and a negative pulse input; the first pulse generator is configured to receive the positive pulse input, the second pulse generator is configured to receive the negative pulse input; and the output stage is configured to generate a positive pulse output responsive to the positive pulse input and to generate a negative pulse output responsive to the negative pulse input. 11. The buffer circuit of claim 1, wherein: the first and second pulse generators are configured to receive a level signal from the input signal; and the output stage is configured to generate a positive pulse output responsive to a rising edge in the input signal and to generate a negative pulse output responsive to a falling edge in the input signal. 12. A buffer circuit for receiving an input signal and for providing an output signal, the buffer circuit comprising: a rising edge pulse generator coupled to receive the input signal and configured to generate a rising edge pulse responsive to a rising edge in the input signal, to receive a delayed version of the rising edge pulse and to terminate the rising edge pulse responsive to the delayed rising edge pulse; a falling edge pulse generator coupled to receive the input signal and configured to generate a falling edge pulse responsive to a falling edge in the input signal, to receive a delayed version of the falling edge pulse and to terminate the falling edge pulse responsive to the delayed falling edge pulse: an output stage coupled to receive the rising edge pulse and the falling edge pulse and configured to output a first logic value for the duration of the first pulse and of second logic value for the duration of the second pulse as the output signal from the buffer circuit; and a reset generator coupled to receive the input signal and configured to generate a rising edge reset signal to enable the rising edge pulse generator responsive to a falling edge in the input signal, and configured to generate a falling edge reset signal to enable the falling edge pulse generator responsive to a rising edge in the input signal. 13. The buffer circuit of claim 12, wherein the output stage comprises a keeper circuit configured to hold the output signal constant between the rising edge pulse and falling edge pulse. 14. The buffer circuit of claim 12, wherein the rising edge pulse generator, the falling edge pulse generator, and the output stage are configured to be large devices. 15. The buffer circuit of claim 12, wherein the rising edge pulse generator and the falling edge pulse generator are configured to receive a level signal from the input signal, and the output stage is configured to generate a level signal as the output signal. 16. The buffer circuit of claim 12, wherein: the input signal comprises a positive pulse input and a negative pulse input; the rising edge pulse generator is configured to receive the positive pulse input; the falling edge pulse generator is configured to receive the negative pulse input; and the output stage is configured to generate a level signal as the output signal. 17. The buffer circuit of claim 12, wherein: the input signal comprises a positive pulse input and a negative pulse input; the rising edge pulse generator is configured to receive the positive pulse input, the falling edge pulse generator is configured to receive the negative pulse input; and the output stage is configured to generate a positive pulse output responsive to the positive pulse input and to generate a negative pulse output responsive to the negative pulse input. 18. The buffer circuit of claim 12, wherein: the rising edge pulse generator and the falling edge pulse generator are configured to receive a level signal from the input signal; and the output stage is configured to generate a positive pulse output responsive to a rising edge in the input signal and to generate a negative pulse output responsive to a falling edge in the input signal. 19. The buffer circuit of claim 12, wherein the buffer receives the input signal from a first a data distribution circuit and provides the output signal to a second data distribution circuit. 20. The buffer of claim 12, further comprising: a rising edge pulse loop generator coupled to receive the rising edge pulse from the rising edge pulse generator and configured to produce a delayed rising edge pulse; a rising edge loop keeper circuit coupled to receive the delayed rising edge pulse and configured to block the rising edge pulse and to disable the rising edge pulse generator; and a rising edge pulse reset coupled to receive the rising edge reset signal and configured to disable the rising edge loop keeper circuit and to re-enable the rising edge pulse generator responsive to the rising edge reset signal. 21. The buffer circuit of claim 20, wherein the width of the rising edge pulse is determined by the amount of delay between the rising edge pulse generator producing the rising edge pulse and the rising edge pulse loop generator producing the delayed rising edge pulse signal. 22. The buffer of claim 12, further comprising: a falling edge pulse loop generator coupled to receive the falling edge pulse from the falling edge pulse generator and configured to produce a delayed falling edge pulse; and a falling edge loop keeper circuit coupled to receive the delayed falling edge pulse and configured to block the falling edge pulse and to disable the falling edge pulse generator; and a falling edge pulse reset coupled to receive the falling edge reset signal and configured to disable the falling edge loop keeper circuit and to re-enable the falling edge pulse generator responsive to the falling edge reset signal. 23. The buffer circuit of claim 22, wherein the width of the second pulse is determined by the amount of delay between the falling edge pulse generator producing the falling edge pulse and the falling edge pulse loop generator producing the delayed falling edge pulse signal. 24. A buffer circuit comprising: an input means for receiving an input signal: a pulse generation means for turning on a pulse signal responsive to a transition in the input signal; an output means for outputting a signal responsive to the pulse signal; a delaying means for delaying the pulse signal to generate a delayed pulse signal; a looping means for turning off the pulse generation means responsive to the delayed pulse signal; and a reset means for resetting the buffer circuit to enable it to respond to a subsequent transition in the input signal, the reset means acting responsive to a complement transition in the input signal. 25. The buffer circuit of claim 24, wherein the duration of the delay generated by the delaying means determines the width of the first pulse signal. 26. The buffer circuit of claim 24, further comprising: a second pulse generation means for turning on a second pulse signal responsive to a complement transition in the input signal; a second delaying means for delaying the second pulse signal to generate a second delayed pulse signal; and a second looping means for turning off the second pulse generation means responsive to the second delayed pulse signal; and the output means is further configured to generate a signal responsive to the second pulse signal. 27. The buffer circuit of 26, wherein the duration of the delay generated by the second delaying means determines the width of the second pulse signal.