초록 ▼

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base si

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

대표청구항 ▼

What is claimed is: 1. A method of designing a programmable logic device (PLD), comprising: a) designing the PLD such that the PLD includes a plurality of logic elements (LE's) arranged in an array; b) designing the PLD such that the PLD includes a base signal routing architecture including a plur

What is claimed is: 1. A method of designing a programmable logic device (PLD), comprising: a) designing the PLD such that the PLD includes a plurality of logic elements (LE's) arranged in an array; b) designing the PLD such that the PLD includes a base signal routing architecture including a plurality of signal routing lines to route signals among the LE's, the base signal routing architecture characterized by a signal routing timing model; c) determining, if the base signal routing architecture is extended across an intellectual property IP-function lock portion incorporated within the array of LE's, an amount by which the resulting timing would differ from the signal routing timing model; and d) based on the determined difference amount, determining whether to design the PLD to extend the signal routing architecture of the PLD across the IP function block portion or to configure the design to include a hole within the base signal routing architecture to accommodate the IP function block portion. 2. The method of claim 1, wherein: step d) includes comparing the determined difference amount to a predetermined threshold amount. 3. The method of claim 1, further comprising: e) designing the PLD such that the PLD includes the hole within the base signal routing architecture, including configuring the design such that the PLD includes the hole having interface circuitry to interface the IP function block to the base signal routing architecture. 4. The method of claim 1, further comprising: e) designing the PLD such that the PLD includes the hole, including designing the PLD such that a portion of the base signal routing architecture is routed across the hole. 5. The method of claim 4, wherein: step e) designing the PLD such that the portion of the base signal routing architecture to be routed across the hole is routed in a physical layer of the PLD other than the physical layer where the base routing architecture is routed in the remainder of the PLD. 6. The method of claim 1, further comprising: e) designing the PLD such that the PLD includes the IP core logic circuitry without interrupting the base signal routing architecture. 7. The method of claim 1, wherein the hole is completely surrounded by the base signal routing architecture. 8. A method of designing a programmable logic device (PLD), comprising: designing the PLD such that the PLD includes a plurality of logic elements (LE's) arranged in an array; designing the PLD such that the PLD includes: a base signal routing architecture including a plurality of signal routing lines to route signals among the LE's, the signal routing lines including short lines and long lines, and at least one intellectual property IP-function block inserted into the array in place of a portion of the LE's, wherein a first subset of the short lines connect to the IP function block and second subset of the short lines terminate at the IP function block while at least one long line passes by the IP function block. 9. The method of claim 8, wherein the short lines have a length less than the length of 8 LE's and the long lines have a length greater than or equal to the length of 8 LE's. 10. The method of claim 8, wherein a third subset of the short lines passes by the IP function block. 11. A method of designing a semiconductor integrated circuit, comprising: a) designing the semiconductor integrated circuit such that the semiconductor integrated circuit includes a plurality of logic elements (LE's) arranged in an array with at least one intellectual property IP-function block inserted into the array; b) designing the semiconductor integrated circuit such that the semiconductor integrated circuit includes a base signal routing architecture connected to the LE's and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is terminated at the IP function block and a second portion of the base signal routing architecture continues past the IP function block. 12. The method of claim 11, further comprising: c) designing the semiconductor integrated circuit such that the semiconductor integrated circuit comprises an interface portion; and d) designing the semiconductor integrated circuit such that a third portion of the base signal routing architecture connects to the IP function block via the interface portion. 13. The method of claim 12, wherein: step a) is such that the base signal routing architecture includes long routing lines and short routing lines, and step b) is such that at least some of the long routing lines continue by the IP function block and at least some of the short routing lines terminate or connect to the IP function block. 14. The method of claim 11, wherein step a) is such that some of the IP function blocks are placed so as not to interrupt the base signal routing architecture. 15. The method of claim 14, wherein: in step a), a decision as to whether the IP function block is placed to interrupt the base signal routing architecture is based on the physical size of the IP function block. 16. The method of claim 15, wherein the decision is based on the physical size as indicated by the die space occupied by the IP function block. 17. The method of claim 15, wherein the decision is based on the physical size as indicated by timing parameters.