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Sockets for "springed" semiconductor devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/00
출원번호 US-0673691 (2003-09-29)
발명자 / 주소
  • Dozier, II,Thomas H.
  • Eldridge,Benjamin N.
  • Grube,Gary W.
  • Khandros,Igor Y.
  • Mathieu,Gaetan L.
  • Pedersen,David V.
  • Stadt,Michael A.
출원인 / 주소
  • FormFactor, Inc.
인용정보 피인용 횟수 : 6  인용 특허 : 59

초록

Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally u

대표청구항

The invention claimed is: 1. A method of electrically connecting an electronic device to a substrate, said method comprising: passing free ends of a plurality of elongate spring contacts attached to said electronic device into a plurality of rigid, conductive recesses in a first surface of said sub

이 특허에 인용된 특허 (59)

  1. Murphy James V. (Warwick RI), Apparatus and method for installation of multi-pin components on circuit boards.
  2. Grabbe Dimitry (2160 Rosedale Ave. Middletown PA 17057), Ball grid array socket.
  3. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Hembree David R. (Boise ID), Carrier for testing an unpackaged semiconductor die.
  4. Wakefield Elwyn P. M. (Bristol GB2), Circuit connection in an electrical assembly.
  5. Oi Kenichi (Osaka JPX), Combined board construction for burn-in and burn-in equipment for use with combined board.
  6. Khandros Igor Y. ; Mathieu Gaetan L., Composite interconnection element for microelectronic components, and method of making same.
  7. Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Sakaguchi Suguru (Chigasaki JPX), Connecting structure for electronic part and method of manufacturing the same.
  8. Reymond Welles (Waterbury CT), Connector system having switching and testing functions using tapered spring contact elements and actuators therefor.
  9. Wood Alan G. (Boise ID) Corbett Tim J. (Boise ID) Chadwick Gary L. (Boise ID) Huang Chender (Boise ID) Kinsman Larry D. (Boise ID), Discrete die burn-in for non-packaged die.
  10. Baumberger John G. (Johnson City NY) Kershaw James J. (Endwell NY) Petrozello James R. (Endicott NY), Dual element electrical contact and connector assembly utilizing same.
  11. O\Connor Bruce (San Diego County CA) Swendrowski Steve (San Diego County CA) Toth Thomas (San Diego County CA), Electrical device transport medium.
  12. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  13. Chang David D. C. (Princeton NJ), Electrical test apparatus and method.
  14. Kazama Toshio,JPX, Electroconductive spring contact unit.
  15. Alcoe David James ; Caletka David Vincent, Electronic component test apparatus with rotational probe and conductive spaced apart means.
  16. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  17. Khandros Igor Y. ; Mathieu Gaetan L., Flexible contact structure with an electrically conductive shell.
  18. Grabbe Dimitry G. (Middletown PA), High density connector for an IC chip carrier.
  19. Janko Bozidar (Portland OR), High density probe.
  20. Ito Akihiko (Hanyu JPX) Kobayashi Yoshihito (Gyoda JPX), IC carrier for use with an IC handler.
  21. Matsuoka Noriyuki (Yokohama JPX) Uratsuji Kazumi (Tokyo JPX), IC socket.
  22. Feldberg Leonard (Spring Valley NY), IDC termination for coaxial cable.
  23. Bamford William C. (Hinsdale IL), Integrated circuit carrier assembly.
  24. Reymond Welles K. (Waterbury CT), Integrated circuit packages using tapered spring contact leads for direct mounting to circuit boards.
  25. Carlomagno William D. (Redwood City CA) Cummings Dennis E. (Placerville CA) Gliga Alexandru S. (San Jose CA), Interconnection of electronic components.
  26. Bargain Raymond (Sartrouville FRX) Riverie Jean (Limours FRX) Ollivier Jean-Francois (Versailles FRX), Intermediate connector for use between a printed circuit card and a substrate for electronic circuits.
  27. Lee Shaw Wei (10410 Miller Ave. Cupertino CA 95014), Known good die test apparatus and method.
  28. Dennis Richard Kay (Etters PA) Hadden Edward Leal (Mechanicsburg PA), Leadless package retaining frame.
  29. Queyssac Daniel G., Low-profile removable ball-grid-array integrated circuit package.
  30. Cushman Robert H. (Princeton Township ; Mercer County NJ), Method and apparatus for gripping multilead articles.
  31. Cushman Robert H. (Princeton NJ), Method for inserting multilead components into printed wiring boards.
  32. Furusawa Keisuke,JPX ; Orimo Takao,JPX, Method for manufacturing a pin and pipe assembly for a bare chip testing socket.
  33. Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Method of exercising semiconductor devices.
  34. Tomoo Murakami JP, Method of mounting a semiconductor device to a substrate.
  35. DiStefano Thomas H. (Monte Sereno CA) Smith ; Jr. John W. (Austin TX), Microelectronics unit mounting with multiple lead bonding.
  36. Geib James F. (Smithfield RI), Minimum insertion force self-cleaning anti-overstress PLCC receiving socket.
  37. Hopkins John R. (Cambridge MD) Ritchie Leon T. (Clearwater FL), Multi terminal low insertion force connector.
  38. Elder Richard A. (Dallas TX) Johnson Randy (Carrollton TX) Frew Dean L. (Garland TX) Wilson Arthur M. (Dallas TX), Non-destructive burn-in test socket for integrated circuit die.
  39. Beaman Brian Samuel ; Fogel Keith Edward ; Lauro Paul Alfred ; Shih Da-Yuan, Pluggable chip scale package.
  40. Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Beck Richard L. (Cupertino CA) Quinn Robert F. (Cupertino CA) Sochor Jerzy R. (San Jose CA), Semiconductor chip interface.
  41. Otsuka Kanji (Higashiyamato JPX) Kato Masao (Hadano JPX) Kumagai Takashi (Isehara JPX) Usami Mitsuo (Ohme JPX) Kuroda Shigeo (Ohme JPX) Sahara Kunizo (Nishitama JPX) Yamada Takeo (Koganei JPX) Miyamo, Semiconductor device having leads for mounting to a surface of a printed circuit board.
  42. Higashi Tatsushi,JPX ; Kuroda Akihiro,JPX ; Tosa Hiroaki,JPX, Semiconductor device with test terminal and IC socket.
  43. Suzuki Kenzo,JPX ; Hiroike Toshimasa,JPX ; Nagano Hiroshi,JPX ; Izawa Hisataka,JPX ; Maru Yasuo,JPX ; Ikeda Shigeo,JPX, Socket for IC and method for manufacturing IC.
  44. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V. ; Stadt Michael A., Sockets for "springed" semiconductor devices.
  45. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L. ; Pedersen David V. ; Stadt Michael A., Sockets for "springed" semiconductor devices.
  46. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pedersen, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
  47. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pederson, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
  48. Dozier ; II Thomas H. ; Eldridge Benjamin N. ; Grube Gary W. ; Khandros Igor Y. ; Mathieu Gaetan L., Sockets for electronic components and methods of connecting to electronic components.
  49. Reymond Welles K. (Waterbury CT), Spring biased tapered contact elements for electrical connectors and integrated circuit packages.
  50. Khandros Igor Y. ; Pedersen David V., Stacking semiconductor devices, particularly memory chips.
  51. Wakamiya Stanley K. (Ellicott City MD) Blake Fred S. (Ellicott City MD) Kurtz John O. (Woodstock MD), Tactile retrieval and insertion and method for electronic components in through-hole printed circuit boards.
  52. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Tandem loop contact for an electrical connector.
  53. Barabi Nasser, Test socket for an IC device.
  54. Ikeya Kiyokazu,JPX ; Padovani Francois A., Test socket for detachable IC chip.
  55. Pfaff Wayne K. (309 Steeplechase Irving TX 75062), Test socket for electronic device packages.
  56. Beaman Brian S. (Hyde Park NY) Doany Fuad E. (Katonah NY) Fogel Keith E. (Bardonia NY) Hedrick ; Jr. James L. (Oakland CA) Lauro Paul A. (Nanuet NY) Norcott Maurice H. (Valley Cottage NY) Ritsko John, Three dimensional high performance interconnection package.
  57. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Three dimensionally interconnected module assembly.
  58. Shiraishi Shogo (Kitakyushu JPX), Universal probe card for use in a semiconductor chip die sorter test.
  59. Khandros Igor Y. ; Pedersen David V., Wafer-level burn-in and test.

이 특허를 인용한 특허 (6)

  1. Park, Chan, Flip-chip packages allowing reduced size without electrical shorts and methods of manufacturing the same.
  2. Seo,Dongweon; Hwang,Juntae, Interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same.
  3. Seo,Dongweon; Hwang,Juntae, Interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same.
  4. Nagano, Shinichi; Yoshida, Shin, Method for bonding metallic terminals by using elastic contact.
  5. Pedersen, David V.; Eldridge, Benjamin N.; Khandros, Igor Y., Socket for making with electronic component, particularly semiconductor device with spring packaging, for fixturing, testing, burning-in or operating such a component.
  6. Miller, Charles A.; Cooper, Timothy E.; Hatsukano, Yoshikazu, Test method for yielding a known good die.
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