초록 ▼

Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature si

Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

대표청구항 ▼

The invention claimed is: 1. A method of forming conductors over a semiconductor body having a top surface in which electrical contact areas are formed comprising the steps of: forming a first inorganic insulating layer having a first value of k over the top surface; forming vias completely through

The invention claimed is: 1. A method of forming conductors over a semiconductor body having a top surface in which electrical contact areas are formed comprising the steps of: forming a first inorganic insulating layer having a first value of k over the top surface; forming vias completely through the first inorganic insulating layer which are in contact with the contact areas; filling the vias through the first inorganic insulating layer with conductive material to form conductive plugs which contact the contact areas; forming a first dielectric insulating layer having a second value of k over the first inorganic insulating layer, said second value of k being lower than said first value of k; forming trenches in the first dielectric insulating layer from a top surface thereof; lining the trenches in the first dielectric insulating layer with a conductive barrier liner layer; filling the trenches in the first dielectric insulating layer with copper to at least a level of a top surface of the first dielectric insulating layer; removing a portion of the copper fill in the trenches so as to recess the copper in the trenches from the top surface of the first dielectric insulating layer; applying a conductive activation layer of Pd over the top surface of the recessed copper; electrolessly and selectively depositing a conductive barrier layer over the conductive activation layer in the trenches, said conductive barrier layer having a top surface which is essentially planar with the top surface of the first dielectric insulating layer, the conductive barrier layer on the top surface of the recessed copper selected from a group consisting of CoP, Co, Ni, NiP, W, Ru, Mo, Cr, Re, V, Mn, Zn, Sn, Pb, and combinations thereof, to work as a Cu diffusion barrier; forming a second dielectric insulating layer having the second value of k over and directly contact with the first dielectric insulating layer; forming vias and trenches in the second dielectric insulating layer and lining same with a conductive barrier liner layer, copper filling, copper recessing, conductive activation applying, and forming a conductive barrier layer over a conductive activation layer as was done with respect to the first dielectric insulating layer; and forming a second inorganic insulating layer having a relatively high k over a top surface of the second dielectric insulating layer. 2. The method of claim 1 wherein the first and second inorganic insulating layers have a k of 3.7 or greater and the first and second dielectric insulating layers have a k of 3.7 or less. 3. The method of claim 2 wherein the first and second inorganic insulating layers are each selected from a group consisting of silicon oxide, boron-doped oxide (BSG), phosphorus-doped oxide (PSG), boron and phosphorus-doped oxide (BPSG), and Fluorine-doped oxide (PSG). 4. The method of claim 1 wherein the conductive material filling the vias in the first inorganic layer is tungsten. 5. The method of claim 1 wherein the conductive barrier liner layers are selected from a group consisting of at least one of a group consisting of Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, and TaSiN. 6. The method of claim 1 wherein the copper is deposited electrolytically. 7. The method of claim 1 wherein the copper is deposited by electrodeposition, CVD and PVD. 8. The method of claim 1 in which the copper over fills the vias and trenches and is planarized to the level of the top surface of the second dielectric insulating layer by chemical-mechanical polishing. 9. The method of claim 1 wherein the step of removing a portion of the copper is achieved by etching in an aqueous copper etching solution. 10. The method of claim 1 wherein the step of removing a portion of the copper is achieved by reactive ion etching. 11. The method of claim 1 further comprising a touch up CMP to the conductive barrier layer. 12. The method of claim 1 further comprising the steps of: forming a plurality of additional dielectric insulating layers of the same dielectric constant as the first dielectric insulating layer over the second dielectric insulating layer; and forming vias and trenches in the plurality of additional dielectric layers and lining with a conductive barrier liner layer, copper filling, copper recessing, conductive activation applying, and forming a conductive barrier over a conductive activation layer as was done with respect to the first dielectric insulating layer. 13. The method of claim 12 wherein each of the additional dielectric insulating layers has a k of about 3.7 or less. 14. A method of forming conductors over a semiconductor body having a top surface in which electrical contact areas are formed comprising the steps of: forming a first silicon oxide layer over the top surface of the semiconductor body; forming vias completely through the first silicon oxide layer which are in contact with the contact areas; filling the vias through the first silicon oxide layer with conductive material to form conductive plugs which contact the contact areas; forming a first insulating layer having a lower k than silicon oxide over the first silicon oxide layer; forming trenches in the first insulating layer from a top surface thereof; lining the trenches in the first insulating layer with a conductive barrier liner layer; filling the trenches in the first insulating layer with copper to at least a level of a top surface of the first insulating layer; removing a portion of the copper fill in the trenches so as to recess the copper in the trenches from the top surface of the first insulating layer; applying a conductive activation layer over top surfaces of the recessed copper; forming a conductive barrier layer over the conductive activation layer, said conductive barrier layer having a top surface which is essentially planar with the top surface of the first insulating layer, the conductive barrier layer on the top surface of the recessed copper selected from a group consisting of CoP, Co, NiP, W, Ru, Mo, Cr, Ref, V, Mn, Zn, Sn, Pb, and combinations thereof; forming a second insulating layer having the same dielectric constant as the first insulating layer over and directly contact with the first insulating layer; forming vias and trenches in the second insulating layer and lining same with a conductive barrier liner layer, copper filling, copper recessing, conductive activation applying, and forming a conductive barrier layer over a conductive activation layer as was done with respect to the first insulating layer; and forming a second silicon oxide layer over a top surface of the second insulating layer. 15. The method of claim 14 further comprising the steps of: forming a plurality of additional insulating layers of the same dielectric constant as the first and second insulating layers over the second insulating layer and below the second silicon oxide layer; and forming vias and trenches in the plurality of additional insulating layers and lining each with a conductive barrier liner, copper filling, copper recessing, conductive activation applying, and forming barrier layers over a conductive activation layer as was done with respect to the second insulating layer. 16. The method of claim 14 further comprising the step of forming a silicon nitride layer over the second silicon oxide layer.