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Interconnect structure for use in an integrated circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/52
출원번호 US-0547926 (2000-04-11)
발명자 / 주소
  • McTeer,Allen
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Dickstein Shapiro Morin &
인용정보 피인용 횟수 : 15  인용 특허 : 21

초록

A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrat

대표청구항

What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. An interconnect structure providing electrical connection in a semiconductor device, said interconnect structure comprising: a first conductive plug; a second conductor plug electrically coupled to said

이 특허에 인용된 특허 (21)

  1. Meckler Gershon (725 Campbell Way Herndon VA 22070), Air conditioning apparatus.
  2. Monma Jun,JPX ; Asai Hironori,JPX, Aluminum nitride wiring substrate and method for production thereof.
  3. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  4. Hause Fred N. ; Bandyopadhyay Basab ; Dawson Robert ; Fulford ; Jr. H. Jim ; Michael Mark W. ; Brennan William S., Dissolvable dielectric method and structure.
  5. Lin Min-Yi,TWX, Dual damascene interconnect structure with reduced parasitic capacitance.
  6. Trivedi Jigish D. ; Iyer Ravi, Local interconnect comprising titanium nitride barrier layer.
  7. Kwon Dong-chul,KRX ; Wee Young-Jin,KRX, Low resistance interconnect for a semiconductor device and method of fabricating the same.
  8. Radhakrishnan Gouri (Culver City CA), Low temperature photolytic deposition of aluminum nitride thin films.
  9. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  10. Nakahashi Masako (Kawasaki JPX) Shirokane Makoto (Tokyo JPX) Yamazaki Tatsuo (Tokyo JPX) Yoshino Hisashi (Yokohama JPX) Hori Akio (Kawasaki JPX) Takeda Hiromitsu (Tokyo JPX), Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same.
  11. Gardner Donald S., Method of fabricating a barrier against metal diffusion.
  12. Numata Ken (Dallas TX), Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layer.
  13. Quek Shyue Fong,MYX ; Ang Ting Cheong,SGX ; Chan Lap ; Loong Sang Yee,SGX, Method to form, and structure of, a dual damascene interconnect device.
  14. Kim Sung C. (Boise ID) Yu Chris C. (Boise ID) Doan Trung T. (Boise ID), Process for depositing aluminum nitride (AlN) using nitrogen plasma sputtering.
  15. Olowolafe Johnson O. (Austin TX) Kawasaki Hisao (Austin TX) Lee Chii-Chang (Austin TX), Process for forming a conductive layer for semiconductor devices.
  16. Meyer George R. (Austin TX), Process for forming a semiconductor device having field isolation.
  17. Sun Shih-Wei (Austin TX), Process for forming semiconductor-on-insulator device.
  18. Li Jian (Ithaca NY) Mayer James W. (Phoenix AZ) Colgan Evan G. (Suffern NY) Gambino Jeffrey P. (Gaylordsville CT), Self-aligned process for capping copper lines.
  19. Maniar Papu D. (Austin TX) Moazzami Reza (Austin TX) Mogab C. Joseph (Austin TX), Semiconductor device having a reducing/oxidizing conductive material.
  20. Ohmi Tadahiro,JPX ; Tsubouchi Kazuo,JPX ; Takewaki Toshiyuki,JPX, Semiconductor device with enhanced thermal conductivity.
  21. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

이 특허를 인용한 특허 (15)

  1. Rozenblat, Avraham; Haimson, Shai; Drori, Rotem; Rotlain, Maor; Horvitz, Dror, Barrier layer for integrated circuit contacts.
  2. Fiordalice,Robert W.; Pintchovski,Faivel, Barrier material formation in integrated circuit structures.
  3. Venezia, Vincent; Mao, Duli; Tai, Hsin-Chih; Qian, Yin; Rhodes, Howard E., CMOS image sensor with heat management structures.
  4. Streck, Christof; Kahlert, Volker, Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride.
  5. Schaff, William J.; Hwang, Jeonghyun; Green, Bruce M., Method of forming an AlN coated heterojunction field effect transistor.
  6. Streck, Christof; Kahlert, Volker, Method of manufracturing increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride.
  7. Ke, Chung Hu; Wang, Ching Ya; Lee, Wen Chin, System and method for forming a semiconductor device source/drain contact.
  8. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  9. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  10. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  11. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  12. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  13. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  14. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  15. McTeer, Allen, Use of AIN as cooper passivation layer and thermal conductor.
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