Updating remote locked cache
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IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0318594
(2002-12-12)
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발명자
/ 주소 |
- Brown,Jeffrey Douglas
- Day,Michael Norman
- Johns,Charles Ray
- Kahle,James Allan
- Shippy,David J.
- Truong,Thuong Quang
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출원인 / 주소 |
- International Business Machines Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
6 |
초록
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A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry i
A system and method are provided for directly accessing a cache for data. A data transfer request is sent to a system bus for transferring data to a system memory. The data transfer request is snooped. A snoop request is sent to a cache. It is determined whether the snoop request has a valid entry in the cache. Upon determining that the snoop request has a valid entry in the cache, the data is caught and sent to the cache for update.
대표청구항
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The invention claimed is: 1. A computer system having one or more processors and a system memory, the computer system comprising: a first processor; a cache coupled to the first processor; a first bus controller; a system bus coupled to both the first bus controller and the system memory, the first
The invention claimed is: 1. A computer system having one or more processors and a system memory, the computer system comprising: a first processor; a cache coupled to the first processor; a first bus controller; a system bus coupled to both the first bus controller and the system memory, the first bus controller sending a data transfer request for transferring data to the system memory via the system bus; a second bus controller coupled to both the cache and the system bus, the second bus controller both snooping the data transfer request and sending a snoop request to the cache; detector means for determining whether the snoop request has a valid entry in the cache; data transmission means for, upon determining that the snoop request has a valid entry in the cache, catching said data from the system bus as said data is being transferred to the system memory and directly sending said data to only the cache for update to maintain a valid entry for said data in the cache, thereby enabling the first processor to directly access said data from the valid entry in the cache; a second processor; and a direct memory access controller (DMAC) coupled to both the second processor and the first bus controller. 2. The computer system of claim 1, further comprising a local memory coupled to the second processor. 3. The computer system of claim 2, wherein the second processor is configured to set up a direct memory access (DMA) transfer whereby the data is transferred from the local memory to the system memory. 4. The computer system of claim 1, wherein the DMAC is configured to send the data transfer request to the first bus controller. 5. The computer system of claim 1, further comprising means for, upon determining that the snoop request has no valid entry in the cache, storing the data in the system memory. 6. The computer system of claim 1, further comprising a cache controller. 7. The computer system of claim 6, wherein the cache controller comprises the means for determining whether the snoop request has a valid entry in the cache. 8. The computer system of claim 1, wherein the cache comprises locked cache lines for valid entries. 9. A method for directly accessing a cache for data in a computer system, the method comprising the steps of: setting up a direct memory access (DMA) transfer whereby the data is transferred from a local memory coupled to a processor to a system memory; sending a data transfer request to a bus controller; snooping the data transfer request; sending a snoop request to a cache; determining whether the snoop request has a valid entry in the cache; and upon determining that the snoop request has a valid entry in the cache, catching said data from a system bus as said data is being transferred to the system memory and directly sending said data to only the cache for update to maintain a valid entry for said data in the cache, thereby enabling a subsequent access of said data directly from the valid entry in the cache. 10. The method of claim 9, further comprising the step of directly accessing the cache for the data. 11. The method of claim 9, further comprising the steps of, upon determining that the snoop request has no valid entry in the cache, storing the data in the system memory. 12. The method of claim 9, further comprising the step of locking the data in the cache. 13. A computer program product for directly accessing a cache for data in a computer system, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer program code for setting up a direct memory access (DMA) transfer whereby the data is transferred from a local memory coupled to a processor to a system memory; computer program code for sending a data transfer request to a bus controller; computer program code for snooping the data transfer request; computer program code for sending a snoop request to a cache; computer program code for determining whether the snoop request has a valid entry in the cache; and computer program code for, upon determining that the snoop request has a valid entry in the cache, catching said data from the system bus as said data is being transferred to the system memory and directly sending said data to only the cache for update to maintain a valid entry for said data in the cache, thereby enabling a subsequent access of said data directly from the valid entry in the cache. 14. The computer program product of claim 13, the computer program further comprising computer program code for directly accessing the cache for the data. 15. The computer program product of claim 13, the computer program further comprising computer program code for, upon determining that the snoop request has no valid entry in the cache, storing the data in the system memory. 16. The computer program product of claim 13, the computer program further comprising computer program code for locking the data in the cache.
이 특허에 인용된 특허 (6)
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Sharma, Debendra Das; Ebner, Sharon M.; Wickeraad, John A.; Cowan, Joe P.; Jackson, Carl H., Apparatus and method for ensuring forward progress in coherent I/O systems.
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Steinbach Andy ; Swanstrom Scott ; Wisor Michael, Architecture and method for controlling a cache memory.
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Zeller Charles P. (Austin TX) Gaskins Darius D. (Austin TX), Cache-based computer system employing a snoop control circuit with write-back suppression.
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Thaller Kurt M. (Acton MA) Metzger Jeffrey A. (Leominster MA) Godiwala Nitin D. (Boylston MA) Maskas Barry A. (Sterling MA), Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system.
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Bohrer, Patrick Joseph; Rajamony, Ramakrishnan; Shafi, Hazim, Method and apparatus for accelerating input/output processing using cache injections.
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Chin Kenneth T. ; Collins Michael J. ; Larson John E. ; Lester Robert A., System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache.
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