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Method and apparatus to resolve instruction starvation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
출원번호 US-0251083 (2002-09-19)
발명자 / 주소
  • Kulick,S. Steven
  • Ram,Rajee S.
  • Tan,Sin Sim
  • Naqib,Rami A.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 10  인용 특허 : 29

초록

Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.

대표청구항

We claim: 1. A method, comprising: determining whether instruction starvation is occurring based upon detecting whether a first transaction from a first agent has not been accepted by a system resource; activating a mechanism to resolve instruction starvation if it is determined that instruction st

이 특허에 인용된 특허 (29)

  1. Munguia Gabriel Roland, Address dependent retry system to program the retry latency of an initiator PCI agent.
  2. Borkenhagen John Michael ; Flynn William Thomas ; Wottreng Andrew Henry, Altering thread priorities in a multithreaded processor.
  3. Bigelow George A. (Boulder CO) Rehage Ted A. (Longmont CO) Shook Frankie S. (Longmont CO), Alternating data buffers when one buffer is empty and another buffer is variably full of data.
  4. Shah Nilesh (Folsom CA) Prasad Rajeev (Folsom CA), Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation.
  5. Kalish David Mark ; Marrash Russell Lee ; Whitlock Gary Carl ; Nguyen Kha, Arbitration system for bus requestors with deadlock prevention.
  6. Astle Brian (Cranbury NJ), Buffer fullness indicator.
  7. Collins Michael J. ; Moriarty Michael P. ; Larson John E. ; Ramsey Jens K., Computer system controller and method with processor write posting hold off on PCI master memory request.
  8. Leach Jerald G. (Houston TX) Simar Laurence R. (Richmond TX), Data communication control by arbitrating for a data transfer control token with facilities for halting a data transfer.
  9. Burns, David W.; Allen, James D.; Upton, Michael D.; Boggs, Darrell D.; Kyker, Alan B., Determination of approaching instruction starvation of threads based on a plurality of conditions.
  10. Kelley, Richard Allen; Neal, Danny Marvin; Thurber, Steven Mark, Enhanced bus arbiter utilizing variable priority and fairness.
  11. Metz ; Jr. Walter C. (Raleigh NC) Rindos ; III Andrew J. (Durham NC), Flow controller for shared bus used by plural resources.
  12. Sera Akihiro (Tokyo JPX) Goukon Kazuhiko (Kawasaki JPX) Shibata Yuji (Kawasaki JPX), I/O control system using buffer full/empty and zero words signals to control DMA read/write commands.
  13. Feal Brice J. (Endicott NY) Hanrahan Donald J. (Endwell NY) Shippy David J. (Endwell NY), Least recently used arbiter with programmable high priority mode and performance monitor.
  14. Willke, II, Theodore L.; Morrow, Warren R., Managing resources in a bus bridge.
  15. Mastronarde, Josh B.; Sreenivas, Aditya; Piazza, Thomas A., Memory arbiter with intelligent page gathering logic.
  16. McTague Michael J. ; Congdon Bradford B., Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed.
  17. Jaramillo Ken ; Knudsen Carl, Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource.
  18. Yang Henry S. (Andover MA) Ramakrishnan Kadangode K. (Maynard MA) Daniely Gady (Jerusalem ILX) Wertheimer Aviad (Jerusalem ILX), Method for assigning priority to receive and transmit requests in response to occupancy of receive and transmit buffers.
  19. Manabe Masao,JPX, PCI bus system wherein target latency information are transmitted along with a retry request.
  20. Flynn William Thomas ; Randolph Jack Chris ; Larsen Troy Dale, Performance monitoring of thread switch events in a multithreaded processor.
  21. Bennett, Joseph A., Preventing starvation of agents on a bus bridge.
  22. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  23. Tobagi Fouad A. (Los Altos CA) Gang ; Jr. Joseph M. (Saratoga CA) Goodrich Allen B. (Mountain View CA), Process for fair and prioritized access to limited output buffers in a multi-port switch.
  24. Leach Jerald G. (Houston TX) Simar Laurence R. (Richmond TX) Davis Alan L. (Houston TX) Tatge Reid E. (Richmond TX), Processing devices with improved addressing capabilities, systems and methods.
  25. Andersen Victor A. (North Dartmouth MA), Signal processor having multiple distributed data buffers.
  26. Carrafiello Michel W. (Hudson NH) Niskala Walter K. (Salem NH) Brown Benjamin J. (Chichester NH), System for minimizing underflowing transmit buffer and overflowing receive buffer by giving highest priority for storage.
  27. Emer Joel S. ; Stamm Rebecca ; Fossum Trggve ; Halstead ; Jr. Robert H. ; Chrysos George Z. ; Tullsen Dean ; Eggers Susan ; Levy Henry M., Thread properties attribute vector based thread selection in multithreading processor.
  28. San Andres Ramon J. ; Choquier Philippe,FRX ; Greenberg Richard G. ; Peyroux Jean-Francois, Transaction replication system and method for supporting replicated transaction-based services.
  29. Zulian Ferruccio,ITX, Unit for arbitration of access to a bus of a multiprocessor system with multiprocessor system for access to a plurality.

이 특허를 인용한 특허 (10)

  1. Maron, William A.; Flemming, Diane Garza; Gholami, Ghadir Robert; Srinivas, Mysore Sathyanarayana; Herescu, Octavian Florin, Bus access moderation system.
  2. Morris, Dale C., Computer processor with fairness monitor.
  3. Johns, Charles R.; Krolak, David J.; Liu, Peichun P.; Ng, Alvan W., Livelock resolution.
  4. Johns,Charles R.; Krolak,David J.; Liu,Peichun P.; Ng,Alvan W., Livelock resolution method.
  5. Nemirovsky, Mario; Musoll, Enrique; Huynh, Jeffrey, Monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads.
  6. Burns, David W.; Venkatraman, K. S., Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time.
  7. Doing, Richard William; Patty, John R.; Testa, Steven Robert; Truong, Thuong Quang, Preventing livelocks in processor selection of load requests.
  8. Johns, Charles R.; Krolak, David J.; Liu, Peichun P.; Ng, Alvan W., Structure for a livelock resolution circuit.
  9. Burns, David W.; Venkatraman, K. S., Thread livelock reduction unit.
  10. Burns, David W.; Venkatraman, K. S., Thread livelock unit.
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