An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a d
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
대표청구항▼
We claim: 1. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing data in a downstream
We claim: 1. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events; and one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal. 2. An integrated circuit, as in claim 1, wherein one or more said stages comprises: a register stage triggered by one or more data triggering events to pass data from one or more upstream stages to one or more downstream stages; and a stall logic circuit passing said delayed stall signal from one or more downstream stages to one or more upstream stages upon receiving one or more stall triggering events, said delayed stall signal selectively inhibiting one or more of said data triggering events. 3. An integrated circuit, as in claim 2, where a local trigger event generator produces said one or more data triggering events responsive to said one or more of said stage triggering events, said data trigger event gated by said delayed stall signal. 4. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events; and one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal. 5. An integrated circuit, as in claim 4, wherein said pipeline is one or more of the following: a) a synchronous pipeline; b) a locally clocked pipeline; c) an interlocked pipeline; and d) an asynchronous pipeline. 6. An integrated circuit, as in claim 4, wherein a portion of said pipeline is one of the following: a) a queue; and b) a first-in, first-out register. 7. An integrated circuit, as in claim 4, further comprising an event generation and distribution network that provides one or more of said stage triggering events to one or more of said stages. 8. An integrated circuit, as in claim 4, wherein a said stage triggering event is one or more of the following: a) a rising edge on a global clock; b) a falling edge on a global clock; c) a rising edge on a local clock; d) a falling edge on a local clock; e) a signal pulse; f) a handshake; g) an event on an asynchronous sequencing signal; and h) an event on a timing signal. 9. An integrated circuit, as in claim 4, further comprising a logic circuit that provides one or more logic signals to one or more stages of one or more said pipelines, said logic signal being one or more of the following: a) a delayed stall signal provided to one or more upstream stages; and b) a delayed valid signal provided to one or more downstream stages. 10. An integrated circuit, as in claim 9, wherein said logic circuit is one or more of the following: a) a combinational logic; b) a sequential logic; c) a state machine; d) a latch; e) a delay element; f) a precharged domino logic; and g) a wire. 11. An integrated circuit, as in claim 9, wherein each of said logic signals is generated by said logic circuit responsive to one or more of the following: a) one or more said downstream stages being stalled; b) one or more said upstream stages being valid; c) one or more of the said stage triggering events; d) one or more stall signals from one or more downstream stages; e) one or more delayed stall signals from one or more downstream stages; f) one or more valid signals from one or more upstream stages; g) one or more delayed valid signals from one or more upstream stages; h) one or more control signals from one or more stages; i) one or more data signals from one or more stages; and j) one or more signals from an environment of said pipeline. 12. An integrated circuit, as in claim 4, wherein one or more stages comprises: a register stage selectively triggered by one or more data triggering events to pass data from one or more upstream stages to one or more downstream stages; a valid logic circuit passing a valid signal from one or more upstream stages to one or more downstream stages upon receiving one or more valid triggering events, said valid signal selectively inhibiting one or more of said data triggering events; and a stall logic circuit passing a stall signal from one or more downstream stages to one or more upstream stages upon receiving one or more stall triggering events, said stall signal selectively inhibiting one or more of said data triggering events. 13. An integrated circuit, as in claim 12, wherein said data triggering event and said valid triggering event are coincident events. 14. An integrated circuit, as in claim 12, where said data triggering event and said stall triggering event are one of the following: a) alternate events; and b) coincident events. 15. An integrated circuit, as in claim 12, where a local trigger event generator produces said one or more data triggering events responsive to said one or more stage triggering events, said data trigger event gated by one or more of the following: a) said valid signal; and b) said stall signal. 16. An integrated circuit as in claim 4 wherein said pipeline is an asynchronous pipeline and said stall signal is an acknowledge signal. 17. An integrated circuit as in claim 4, wherein at least one stage is one or more of the following: a) a stage with one storage node; b) a transparent latch stage; c) a precharged domino logic stage; d) a stage with two or more storage nodes; e) a master/slave stage; f) a flip/flop stage; g) a sense-amplifier latch stage; and h) a pulsed latch stage. 18. An integrated circuit as in claim 4, wherein a pair of adjacent said stages form one or more of the following: a) a stage with two storage nodes; b) a master/slave stage; c) a flip/flop stage; d) a sense-amplifier latch stage; and e) a pulsed latch stage. 19. An integrated circuit as in claim 4, wherein alternate pipeline stages latch at alternate stage triggering events. 20. An integrated circuit as in claim 4, wherein two or more pipeline stages latch at one or more coincident stage triggering events. 21. An integrated circuit as in claim 4, wherein one or more of said stages is a precharged domino logic stage that is held in a non-precharge and non-evaluate mode. 22. An integrated circuit as in claim 21, wherein said precharged domino logic stage evaluates selectively based on said valid signal. 23. An integrated circuit as in claim 21, wherein said precharged domino logic stage alternately precharges and evaluates responsive to alternate stage triggering events. 24. An integrated circuit as in claim 4, wherein said at least one stage is a pulsed latch stage and said pulsed latch stage is a master/slave stage, where in unstalled portions of said pipeline the master latch of said pulsed latch stage is transparent and the slave latch of said pulsed latch stage is pulsed, and in stalled portions of said pipeline said master latch of said pulsed latch stage is opaque. 25. An integrated circuit as in claim 4, wherein a pair of adjacent said stages form a pulsed latch stage and said pulsed latch stage is a master/slave stage, where in unstalled portions of said pipeline the slave latch of said pulsed latch stage is transparent and the master latch of said pulsed latch stage is pulsed, and in stalled portions of said pipeline said slave latch of said pulsed latch stage is opaque. 26. A method of operating stages of a synchronous pipeline, said method comprising the steps of: a) checking a stall-out signal for a previously asserted stall condition; b) passing an incoming stall signal through a stall-in latch to a stall-out latch; c) passing incoming data through an upstream pipeline stage in an opposite direction of said incoming stall signal; d) checking an output of said stall-in latch for an asserted stall condition; e) passing said output of said stall-in latch through said stall-out latch as said stall-out signal; f) passing data from said upstream pipeline stage through a current pipeline stage in an opposite direction of said incoming stall signal; and g) returning to step (a). 27. A method of operating stages of a synchronous pipeline as in claim 26, wherein when a stall condition is asserted in the checking step (d), step (d) further comprises the steps of: d1) passing said output of said stall-in latch through said stall-out latch as said stall-out signal; and d2) returning to step (a), whereby said current pipeline stage is stalled until said stall condition is no longer found asserted in step (d). 28. A method of operating stages of a synchronous pipeline as in claim 27, wherein when a stall condition is asserted in the checking step (a), step (a) further comprises the steps of: a1) passing said incoming stall signal through said stall-in latch to said stall-out latch; and a2) continuing to step (d), whereby said upstream pipeline stage is stalled until said stall condition is no longer found asserted in step (a). 29. A method of operating stages of a synchronous pipeline, said method comprising the steps of: a) checking an output pipeline stage for valid data and only when valid data is found in said output pipeline, passing an incoming stall signal through a stall-in latch to a stall-out latch; b) checking a stall-out signal from said stall-out latch for an upstream asserted stall condition; c) passing incoming valid data through an input pipeline stage in an opposite direction of said incoming stall signal; d) checking said input pipeline stage for valid data and only when valid data is found in said input pipeline, passing said output of said stall-in latch through said stall-out latch as said stall-out signal; e) checking an output of said stall-in latch for an asserted stall condition; f) passing valid data through said output pipeline stage in an opposite direction of said incoming stall signal; and g) returning to step (a). 30. A method of operating stages of a synchronous pipeline as in claim 29, wherein a valid data out latch is checked in step (a) to determine if valid data is in said output pipeline stage and, wherein a valid data latch is checked in step (d) to determine if valid data is in said input pipeline stage. 31. A method of operating stages of a synchronous pipeline as in claim 30, wherein whenever a stall condition is not found previously asserted in step (b), a valid data input signal is passed through said valid data latch. 32. A method of operating stages of a synchronous pipeline as in claim 31, wherein whenever a stall condition is not found previously asserted in step (b) and valid data is being provided to said input pipeline stage, valid data is passed through said input pipeline stage. 33. A method of operating stages of a synchronous pipeline as in claim 31, wherein whenever a stall condition is not found previously asserted in step (e), an output of said valid data latch is passed through said valid data out latch. 34. A method of operating stages of a synchronous pipeline as in claim 33, wherein whenever a stall condition is not found previously asserted in step (e), and valid data is in said input pipeline stage, valid data is passed through said output pipeline stage. 35. A method of operating stages of a synchronous pipeline as in claim 31, wherein when a stall condition is asserted in the checking step (e), step (e) further comprises returning to step (a), whereby said output pipeline stage is stalled until said stall condition is no longer found asserted. 36. A method of operating a synchronous pipeline as in claim 35, wherein when a stall condition is asserted in the checking step (b), step (b) further comprises continuing to step (d), whereby said input pipeline stage is stalled until said stall condition is no longer found asserted. 37. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events; one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal; and a logic circuit generating delayed stall signals and said delayed valid signals using a handshake protocol based on one or more stall signals and one or more valid signals such that said handshake interlocks the passing of valid data between two or more adjacent stages in said pipeline, wherein one of the stages passes data only when said data is valid and when said stage is not stalled, said stage stalling only if said stage stores valid data and there is a stall condition at said stage. 38. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events; and one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal, wherein during a stall condition, one or more stages upstream of said stall condition continue unstalled and effective storage capacity of said pipeline is increased in one or more of said stalled stages. 39. An integrated circuit comprising: one or more pipelines, each pipeline having two or more stages; one or more triggering inputs on one or more of said stages, said triggering inputs receiving one or more stage triggering events; one or more of said stages passing only valid data in a downstream direction through one or more of said pipelines responsive to one or more of said stage triggering events; one or more stall inputs on one or more of said stages, said stall inputs receiving one or more delayed stall signals, each delayed stall signal occurring a delay time later than a stall signal at one or more downstream stages, and said each delayed stall signal selectively stalling one or more of said stages that receive said each delayed stall signal; a logic circuit generating delayed stall signals using a handshake protocol based on one or more stall signals such that said handshake interlocks the passing of data between two or more adjacent stages in said pipeline, providing a progressive, stage by stage, stalling of said pipeline, where one or more of the upstream stages is stalled said delay time later than the adjacent downstream stage. 40. An integrated circuit, as in claim 39, where said delay time is any one or more of the following: a cycle, a half cycle, a computation cycle, a half computation cycle, a clock cycle, and a half clock cycle.
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이 특허에 인용된 특허 (7)
Furber Stephen Byram,GBX, Dynamic logic pipeline control.
Jacobson, Hans M.; Bose, Pradip; Buyuktosunoglu, Alper; Cook, Peter William; Emma, Philip George; Kudva, Prabhakar N.; Schuster, Stanley Everett, Method and structure for short range leakage control in pipelined circuits.
Idgunji, Sachin Satish; Das, Shidhartha; Bull, David Michael; Aitken, Robert Campbell, Apparatus and method for detecting an approaching error condition.
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