Multilevel copper interconnect with double passivation
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/4763
H01L-021/02
출원번호
US-0721920
(2003-11-24)
발명자
/ 주소
Ahn,Kie Y.
Forbes,Leonard
Eldridge,Jerome M.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
Schwegman, Lundberg, Woessner &
인용정보
피인용 횟수 :
15인용 특허 :
196
초록▼
Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit assembly, e.g., forming multilaye
Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit assembly, e.g., forming multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the multilayer metal lines, then oxidized. An insulator is deposited to fill interstices created by air gaps between the multilayer metal lines. In one embodiment, forming multilayer metal lines includes a conductor bridge level. In one embodiment, forming a silicide layer on the multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300-500 degrees Celsius. In one embodiment, a metal layer is formed on the oxided silicide layer. The metal layer includes one of Aluminum, Chromium, Titanium, Zirconium and Aluminum oxide.
대표청구항▼
We claim: 1. A method for forming multilevel wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer metal lines; oxidizing the silicide
We claim: 1. A method for forming multilevel wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer metal lines; oxidizing the silicide layer; and depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer metal lines. 2. The method of claim 1, wherein forming a number of multilayer metal lines includes a first conductor bridge level. 3. The method of claim 1, wherein forming a silicide layer on the number of multilayer metal lines includes using pyrolysis of a dilute silane ambient at a temperature of approximately 325 degrees Celsius. 4. The method of claim 3, wherein oxidizing the silicide layer includes using a plasma anodization process in an oxygen plasma in order to form a passivating layer for hermetic sealing of the number of multilayer metal lines. 5. The method of claim 1, wherein depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer metal lines includes depositing a low dielectric constant insulator in a single step. 6. A method for forming multilevel wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer metal lines; nitriding the silicide layer; and depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer metal lines. 7. The method of claim 6, wherein forming a number of multilayer metal lines includes a first conductor bridge level. 8. The method of claim 6, wherein forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane in the presence of a dopant in order to form a lightly doped silicide layer. 9. The method of claim 8, wherein nitriding the silicide layer includes using a plasma anodization process in a nitrogen plasma in order to form a passivating layer for hermetic sealing of the number of multilayer metal lines. 10. The method of claim 6, wherein forming the number of multilayer metal lines includes forming a number of metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold. 11. The method of claim 6, wherein forming the number of multilayer metal lines includes forming the number of multilayer metal lines using electroless plating. 12. A method for forming multilayer wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer Copper metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer Copper metal lines; oxidizing the silicide layer; and depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer Copper metal lines. 13. The method of claim 12, wherein forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300 and 500 degrees Celsius in the presence of a dopant in order to form a heavily doped silicide layer. 14. The method of claim 13, wherein oxidizing the silicide layer includes using a plasma anodization process in an oxygen plasma in order to form a passivating layer for hermetic sealing of the number of multilayer Copper metal lines and to add mechanical strength to the number of multilayer Copper metal lines. 15. The method of claim 12, wherein the method further includes depositing a layer of Aluminum on the number of multilayer Copper metal lines subsequent to oxidizing the silicide layer. 16. The method of claim 15, wherein depositing a layer of Aluminum includes depositing a layer of Aluminum using a low pressure chemical vapor deposition process (LPCVD) and forming Aluminum films from trimethylamine complexes of alane as precursors at temperatures of approximately 180 degrees Celsius in a hot walled system. 17. The method of claim 15, wherein the method further includes partially converting the Aluminum layer to Aluminum oxide by oxidation in an oxygen-containing ambient. 18. The method of claim 12, wherein the method further includes depositing a metal layer selected from the group consisting of Chromium, Titanium, and Zirconium on the number of multilayer Copper metal lines subsequent to oxidizing the silicide layer. 19. A method for forming multilayer wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer Copper metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer Copper metal lines; oxidizing the silicide layer; depositing a layer of Aluminum on the oxidized silicide layer; and depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer Copper metal lines. 20. The method of claim 19, wherein forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300 and 500 degrees Celsius. 21. The method of claim 19, wherein oxidizing the silicide layer includes using a plasma anodization process in an oxygen plasma in order to form a passivating layer for hermetic sealing of the number of multilayer Copper metal lines and to add mechanical strength to the number of multilayer Copper metal lines. 22. The method of claim 19, wherein depositing a layer of Aluminum includes depositing a layer of Aluminum using a low pressure chemical vapor deposition process (LPCVD) and forming Aluminum films from trimethylamine complexes of alane as precursors at temperatures of approximately 180 degrees Celsius in a hot walled system. 23. The method of claim 19, wherein the method further includes converting the Aluminum layer to Aluminum oxide by oxidation in an oxygen-containing ambient. 24. The method of claim 23, wherein the method further includes thermally oxidizing the Aluminum layer at approximately 100 degrees Celsius in one atmosphere of oxygen to form a passivating layer of Al2O3 having a thickness of approximately 20 Angstroms (Å). 25. The method of claim 19, wherein oxidizing the silicide layer includes a low temperature oxidation process using a magnetically excited plasma oxidation process. 26. A method for forming multilayer wiring interconnects in an integrated circuit assembly, comprising: forming a number of multilayer Copper metal lines separated by a number of air gaps above a substrate; forming a silicide layer on the number of multilayer Copper metal lines; nitriding the silicide layer; depositing a layer of Aluminum on the oxidized silicide layer; and depositing a low dielectric constant insulator to fill a number of interstices between the number of multilayer Copper metal lines. 27. The method of claim 26, wherein forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300 and 500 degrees Celsius. 28. The method of claim 26, wherein nitriding the silicide layer includes reacting an N2 or NH3 plasma with the silicide layer at temperatures below 200 degrees Celsius in order to form a thin layer of silicon nitride Si3N4 having a thickness between 50 and 200 Angstroms (Å). 29. The method of claim 26, wherein depositing a layer of Aluminum includes depositing a layer of Aluminum using a low pressure chemical vapor deposition process (LPCVD) and forming Aluminum films from trimethylamine complexes of alane as precursors at temperatures of approximately 180 degrees Celsius in a hot walled system. 30. The method of claim 26, wherein the method further includes converting the Aluminum layer to Aluminum oxide by oxidation in an oxygen-containing ambient. 31. The method of claim 30, wherein the method further includes thermally oxidizing the Aluminum layer at approximately 100 degrees Celsius in one atmosphere of oxygen to form a passivating layer of Al2O3 having a thickness of approximately 20 Angstroms (Å). 32. The method of claim 26, wherein forming a number of multilayer Copper metal lines above a substrate includes forming the number of multilayer Copper metal lines using electroless plating. 33. A method, comprising: forming a metal line air-bridge structure from a number of multilayer metal lines that connect to a number of silicon devices in a substrate; covering exposed surfaces of the air-bridge structure with a silicide layer; hermetically sealing the underlying metal lines with an oxide layer on the silicide layer and the silicide layer; and forming a low dielectric constant insulator in the number of interstices. 34. The method of claim 33, wherein forming a metal line air-bridge structure includes forming the number of multilayer metal lines from a group consisting of Aluminum, Copper, Silver, and Gold. 35. The method of claim 33, wherein forming a metal line air-bridge structure includes forming a first conductor bridge level. 36. A method, comprising: connecting a number of multilayer metal lines to a number of silicon devices in a substrate; forming a lightly doped silicide layer on the number of multilayer metal lines; hermetically sealing underlying metal lines with the silicide layer and an oxide layer on the silicide layer; forming a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and wherein the silicide layer on the number of multilayer metal lines. 37. A method, comprising: forming a metal line air-bridge structure, which has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure and connects to a number of silicon devices in a substrate; covering the exposed surfaces of the air-bridge structure with a silicide layer; hermetically sealing metal lines of the air-bridge structure underlying a nitride layer on the silicide layer; and providing a low dielectric constant insulator in the number of interstices. 38. The method of claim 37, wherein forming a metal line air-bridge structure includes forming a number of multilayer metal lines from a group consisting of Aluminum, Copper, Silver, and Gold. 39. A method, comprising: connecting a number of multilayer metal lines to a number of silicon devices in a substrate; forming a heavily doped silicide layer on the number of multilayer metal lines; hermetically sealing metal lines using a nitride layer, which underlie the silicide layer, with nitride and silicide layers; forming a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate. 40. A method, comprising: forming a metal line air-bridge structure, which connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure, with a number of multilayer Copper lines; a silicide layer covering the exposed surfaces of the air-bridge structure with a silicide layer; forming an oxide layer on the silicide layer overlying the metal lines so as to hermetically seal the underlying metal lines; forming a metal layer on the oxide layer; and forming a low dielectric constant insulator in the number of interstices. 41. The method of claim 40, wherein forming a metal line air-bridge structure includes forming a metal layer selected from the group consisting of Aluminum, Chromium, Titanium, and Zirconium. 42. The method of claim 41, wherein forming a metal layer includes forming a layer of Aluminum oxide. 43. A method, comprising: forming one or more transistors in a substrate; forming a metal line air-bridge structure, which connects to one or more of the transistors in the substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure, from a number of multilayer Copper lines; covering the exposed surfaces of the air-bridge structure with a suicide layer; hermetically sealing underlying metal lines with the silicide layer and an oxide layer on the silicide layer; forming a layer of partially oxidized Aluminum on the oxide layer; and forming a low dielectric constant insulator in the number of interstices. 44. The method claim 43, wherein forming a layer of partially oxidized Aluminum on the oxide layer includes preventing localized Copper corrosion in the number of multilayer Copper lines connecting to one or more of the transistors in the substrate. 45. The method of claim 43, wherein covering the exposed surfaces of the air-bridge structure with a silicide layer includes forming a polycrystalline layer at a temperature below 150 degrees Celsius using an electron cyclotron resonance plasma enhanced chemical vapor deposition process (ECR PECVD). 46. The method of claim 43, wherein forming a layer of partially oxidized Aluminum includes forming a layer of Al2O 3 having a thickness of approximately 20 Angstroms (Å). 47. A method, comprising: a substrate including one or more transistors; forming a metal line air-bridge structure that connects to one or more of the transistors in the substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure from a number of multilayer Copper lines; covering the exposed surfaces of the air-bridge structure with a silicide layer; forming a nitride layer on the silicide layer so as to provide a hermetic seal of the underlying metal lines; forming a layer of partially oxidized Aluminum on the nitride layer; and forming a low dielectric constant, first insulator in the number of interstices. 48. The method of claim 47, wherein forming the nitride layer includes forming a thin layer of silicon nitride Si3N4 having a thickness between 50 and 200 Angstroms (Å) formed at temperatures below 200 degrees Celsius. 49. The method of claim 47, wherein forming a layer of partially oxidized Aluminum includes a passivating layer of Al2 O3 having a thickness of approximately 20 Angstroms (Å) formed at approximately 100 degrees Celsius in one atmosphere of oxygen. 50. The method of claim 47, wherein forming a metal line air-bridge structure from a number of multilayer Copper lines includes electroless plating the multilayer Copper lines and forming a second insulator layer on the first insulator layer in the number of interstices. 51. The method of claim 50, wherein forming the first insulator layer includes: forming a suicide layer on the number of multilayer Copper lines; and forming an oxide layer on the silicide layer so as to hermetically seal the underlying metal lines. 52. The method of claim 50, wherein forming first insulator layer includes: forming a suicide layer on the number of multilayer Copper lines; and forming a nitride layer on the silicide layer such that the nitride and silicide layers provide a hermetic seal of the underlying metal lines. 53. The method of claim 50, wherein forming a metal line air-bridge structure from a number of multilayer Copper lines includes forming a metal layer on the first insulator layer. 54. The method of claim 53, wherein forming a metal layer includes forming a layer of Al2O3 having a thickness of approximately 20 Angstroms (Å). 55. The system of claim 53, wherein forming a metal layer includes forming a metal layer selected from the group consisting of Aluminum, Chromium, Titanium, and Zirconium. 56. A method, comprising: providing one or more transistors in a substrate; forming, from a number of multilayer Copper lines, a metal line air-bridge structure that connects to one or more of the transistors in the substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; covering the exposed surfaces of the air-bridge structure with a silicide layer; hermetically sealing, with an oxide layer and the silicide layer, the underlying metal lines; forming a metal layer on the oxide layer; forming a low dielectric constant insulator in the number of interstices; and coupling an integrated memory circuit including the metal line air-bridge structure to a processor. 57. The method of claim 56, wherein hermetically sealing includes preventing localized Copper corrosion in the number of multilayer Copper lines connecting to one or more of the transistors in the substrate. 58. The method of claim 56, wherein covering the exposed surfaces of the air-bridge structure with a silicide layer includes forming a polycrystalline layer at a temperature below 150 degrees Celsius using an electron cyclotron resonance plasma enhanced chemical vapor deposition process (ECR PECVD). 59. The method of claim 56, wherein forming the metal layer includes forming a layer of Al2O3 having a thickness of approximately 20 Angstroms (Å). 60. The method of claim 56, wherein forming the metal layer includes forming a metal layer selected from the group consisting of Aluminum, Chromium, Titanium, and Zirconium. 61. A method, comprising: forming one or more transistors on a substrate; forming, with a number of multilayer metal lines, a metal line air-bridge structure that connects to one or more of the transistors in the substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; covering the exposed surfaces of the air-bridge structure with a silicide layer; providing an oxide layer on the silicide layer so as to provide a hermetic seal of the underlying metal lines with the oxide and suicide layers; forming a layer of Al2O3 having a thickness of approximately 20 Angstroms (Å) on the oxide layer; forming a low dielectric constant insulator in the number of interstices; and coupling an integrated memory circuit including the metal line air-bridge structure to a processor. 62. The method of claim 61, wherein forming, with a number of multilayer metal lines, a metal line air-bridge structure includes forming a number of multilayer metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold. 63. The method of claim 61, wherein forming a low dielectric constant insulator includes forming a polyimide layer. 64. The method of claim 63, wherein forming the polyimide layer includes forming a foamed polyimide layer. 65. A method, comprising: forming one or more transistors on a substrate; connecting a number of multilayer metal lines to one or more of the transistors in the substrate; forming a lightly doped silicide layer on the number of multilayer metal lines; forming an oxide layer on the silicide layer so as to hermetically seal the underlying metal lines; forming a layer of Al2O3 having a thickness of approximately 20 Angstroms (Å) on the oxide layer; forming a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate; and coupling an integrated memory circuit including the metal line air-bridge structure to a processor. 66. The method of claim 65, wherein connecting the number of multilayer metal lines connecting to one or more transistors in the substrate includes forming a first conductor bridge level. 67. A method, comprising: forming, from a number of multilayer metal lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; covering the exposed surfaces of the air-bridge structure with a silicide layer; hermetically sealing the underlying metal lines with the silicide layer and an oxide layer on the silicide layer; and substantially filling the number of interstices with a low dielectric constant insulator. 68. A method, comprising: forming, from a number of multilayer metal lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; covering the exposed surfaces of the air-bridge structure with a silicide layer; forming an oxide layer converted from and located on the silicide layer so as to provide a hermetic seal of the underlying metal lines; and forming a low dielectric constant insulator in the number of interstices. 69. A method, comprising: forming, from a number of multilayer metal lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; providing a silicide layer covering the exposed surfaces of the air-bridge structure; forming a nitride layer on the silicide layer wherein the nitride and silicide layers provide a hermetic seal of the underlying metal lines; and substantially filling the number of interstices with a low dielectric constant insulator. 70. A method, comprising: forming, from a number of multilayer metal lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; providing a silicide layer covering the exposed surfaces of the air-bridge structure; forming a nitride layer converted from and located on the silicide layer wherein the nitride and silicide layers provide a hermetic seal of the underlying metal lines; and forming a low dielectric constant insulator in the number of interstices. 71. A method, comprising: forming, with a number of multilayer Copper lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; forming a silicide layer covering the exposed surfaces of the air-bridge structure; forming an oxide layer on the silicide layer wherein the oxide and silicide layers provide a hermetic seal of the underlying metal lines; forming a metal layer on the oxide layer; and substantially filling the number of interstices with a low dielectric constant insulator. 72. A method, comprising: forming, with a number of multilayer Copper lines, a metal line air-bridge structure that connects to a number of silicon devices in a substrate and has a number of top, bottom, and side exposed surfaces adjacent to a number of interstices in the air-bridge structure; forming a silicide layer covering the exposed surfaces of the air-bridge structure; forming an oxide layer converted from and located on the silicide layer wherein the oxide and silicide layers provide a hermetic seal of the underlying metal lines; forming a metal layer on the oxide layer; and forming a low dielectric constant insulator in the number of interstices.
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이 특허에 인용된 특허 (196)
Wong Lawrence D., Air gap based low dielectric constant interconnect structure and method of making same.
Grensing Fritz C. (Perrysburg OH) Marder James M. (Shaker Heights OH) Brophy Jere H. (Chagrin Falls OH), Aluminum alloys containing beryllium and investment casting of such alloys.
Grant Larry A. (Saratoga CA) Marder James M. (Shaker Heights OH) Wright Wayne L. (San Jose CA), Aluminum-beryllium alloys having high stiffness and low thermal expansion for memory devices.
Lu Jiong Ping ; Hwang Ming ; Anderson Dirk N. ; Kittl Jorge A. ; Tsai Hun-Lian, CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes.
Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
Harper James M. E. (Yorktown Heights NY) Holloway Karen L. (Mount Kisco NY) Kwok Thomas Y. (Westwood NJ), Copper alloy metallurgies for VLSI interconnection structures.
Kermani Ahmad (Fremont CA) Johnsgard Kristian E. (San Jose CA) Galewski Carl (Berkeley CA), Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure.
Ingraham Anthony P. ; Kehley Glenn L. ; Sathe Sanjeev B. ; Slack John R., Integrated, multi-chip, thermally conductive packaging device and methodology.
Aitken John M. (Mahopac NY) Beyer Klaus D. (Poughkeepsie NY) Crowder Billy L. (Putnam Valley NY) Greco Stephen E. (Lagrangeville NY), Larce scale IC personalization method employing air dielectric structure for extended conductors.
Sachdev Krishna Gandhi ; Hummel John Patrick ; Kamath Sundar Mangalore ; Lang Robert Neal ; Nendaic Anton ; Perry Charles Hampton ; Sachdev Harbans, Low TCE polyimides as improved insulator in multilayer interconnect structures.
Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
Keyser Thomas (Palm Bay FL) Cairns Bruce R. (Los Altos Hills CA) Anand Kranti V. (Sunnyvale CA) Petro William G. (Cupertino CA) Barry Michael L. (Palo Alto CA), Low temperature plasma nitridation process and applications of nitride films formed thereby.
Brors Daniel L. (Los Altos Hills CA) Fair James A. (Mountain View CA) Monnig Kenneth A. (Palo Alto CA), Method and apparatus for deposition of tungsten silicides.
Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
Omstead Thomas R. ; Wongsenakhum Panya ; Messner William J. ; Nagy Edward J. ; Starks William ; Moslehi Mehrdad M., Method and system for dispensing process gas for fabricating a device on a substrate.
Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
Cherng Meng-Jaw,TWX ; Li Pei-Wen,TWX, Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices.
Abt Norman E. (Burlingame CA) Moazzami Reza (Oakland CA) Nissan-Cohen Yoav (Zichren Ya\akov ILX), Method for forming a ceramic oxide capacitor having barrier layers.
Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Wood Alan G. (Boise ID), Method for forming contact pins for semiconductor dice and interconnects.
Cooper Kent J. (Austin TX) Lin Jung-Hui (Austin TX) Roth Scott S. (Austin TX) Roman Bernard J. (Austin TX) Mazure Carlos A. (Austin TX) Nguyen Bich-Yen (Austin TX) Ray Wayne J. (Austin TX), Method for forming contact to a semiconductor device.
Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
Fitzsimmons John A. (Poughkeepsie NY) Havas Janos (Hopewell Junction NY) Lawson Margaret J. (Newburgh NY) Leonard Edward J. (Fishkill NY) Rhoads Bryan N. (Pine Bush NY), Method for forming patterned films on a substrate.
van Laarhoven Josephus M. F. G. (Eindhoven NLX) de Bruin Leendert (Eindhoven NLX) van Arendonk Anton P. M. (Eindhoven NLX), Method of enabling electrical connection to a substructure forming part of an electronic device.
Thomas Michael E. (Cupertino CA) Chinn Jeffrey D. (Foster City CA), Method of fabricating a high performance interconnect system for an integrated circuit.
Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Method of forming a semiconductor structure having an air region.
Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.
Miyauchi Nobuaki (San Diego CA) Yonemasu Hiroshi (San Diego CA) Cho Bakji (San Diego CA), Method of using a contamination shield during the manufacture of EPROM semiconductor package windows.
Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
Zaidel Simon A. (Manlius NY) Alcorn Terrence S. (Liverpool NY) Kopp William F. (Liverpool NY) Pifer George C. (North Syracuse NY), Process for making air bridges for integrated circuits.
Paul A. Farrar, Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy.
Ping-Chuan Wang ; Ronald G. Filippi ; Robert D. Edwards ; Edward W. Kiewra ; Roy C. Iggulden, Process of enclosing via for improved reliability in dual damascene interconnects.
Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
Pfeifer Friedrich (Bruchkbel DEX) Behnke Wernfried (Hanau DEX), Reducing magnetic hysteresis losses in cores of thin tapes of soft magnetic amorphous metal alloys.
Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
Dennison Charles H. ; Doan Trung T., Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein.
Blalock Guy T. ; Howard Bradley J., Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures.
Hughes Henry G. (Scottsdale AZ) Lue Ping-Chang (Scottsdale AZ) Robinson Frederick J. (Scottsdale AZ), Semiconductor device having a low permittivity dielectric.
Xu Zheng ; Forster John ; Yao Tse-Yong, Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches.
Fitch Jon T. (Austin TX) Maniar Papu (Austin TX) Witek Keith E. (Austin TX) Gelatos Jerry (Austin TX) Moazzami Reza (Austin TX) Ajuria Sergio A. (Austin TX), Semiconductor structure having an air region and method of forming the semiconductor structure.
Rathore Hazara S. ; Dalal Hormazdyar M. ; McLaughlin Paul S. ; Nguyen Du B. ; Smith Richard G. ; Swinton Alexander J. ; Wachnik Richard A., Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity.
Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
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