초록 ▼

A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to

A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

대표청구항 ▼

What is claimed is: 1. A semiconductor wafer including a plurality of semiconductor device components, a protective element on selected portions of each semiconductor device component of the plurality, the protective element on one of the plurality of semiconductor device components including a plu

What is claimed is: 1. A semiconductor wafer including a plurality of semiconductor device components, a protective element on selected portions of each semiconductor device component of the plurality, the protective element on one of the plurality of semiconductor device components including a plurality of adjacent, mutually adhered regions comprising the same material. 2. The semiconductor wafer of claim 1, wherein the protective element comprises a thermoplastic material. 3. The semiconductor wafer of claim 2, wherein the thermoplastic material comprises an adhesive. 4. The semiconductor wafer of claim 1, wherein at least one protective element substantially covers an active surface of a corresponding semiconductor device component of the plurality of semiconductor device components. 5. The semiconductor wafer of claim 4, wherein each protective element substantially covers an active surface of a corresponding semiconductor device component of the plurality of semiconductor device components. 6. The semiconductor wafer of claim 1, wherein the protective element comprises a plurality of superimposed, contiguous, mutually adhered layers. 7. The semiconductor wafer of claim 6, wherein each protective element comprises a plurality of superimposed, contiguous, mutually adhered layers. 8. The semiconductor wafer of claim 6, wherein all layers of the plurality of superimposed, contiguous, mutually adhered layers that underlie an outermost layer of the plurality of superimposed, contiguous, mutually adhered layers comprise the same material. 9. The semiconductor wafer of claim 1, wherein the protective element is substantially discontinuous from protective elements on adjacent semiconductor device components. 10. A semiconductor device component, comprising: a substrate with at least one conductor on an active surface thereof; and a plurality of layers of at least semisolid photopolymer material on the active surface, the plurality of layers being superimposed, contiguous, and mutually adhered, each layer of the plurality of layers being substantially free of voids and air pockets, the at least one conductor being electrically exposed through the plurality of layers. 11. The semiconductor device component of claim 10, wherein the at least one conductor is laterally surrounded by the at least semisolid photopolymer material of at least some layers of the plurality of layers. 12. The semiconductor device component of claim 11, wherein the at least one conductor is recessed beneath an outermost layer of the plurality of layers. 13. The semiconductor device component of claim 10, wherein a surface of an outermost layer of the plurality of layers is planar. 14. The semiconductor device component of claim 10, wherein a surface of an outermost layer of the plurality of layers is substantially parallel to the active surface. 15. The semiconductor device component of claim 10, wherein the substrate comprises a semiconductor die. 16. The semiconductor device component of claim 10, wherein the substrate comprises a wafer with a plurality of semiconductor device components. 17. The semiconductor device component of claim 16, wherein each of the plurality of layers exhibits a discontinuous region located over streets of the wafer between adjacent semiconductor device components. 18. The semiconductor device component of claim 17, wherein each of the plurality of layers substantially covers an active surface of a corresponding substrate. 19. The semiconductor device component of claim 10, wherein at least an outermost layer of the plurality of layers comprises an adhesive material. 20. The semiconductor device component of claim 19, wherein the adhesive material comprises thermoplastic material. 21. The semiconductor device component of claim 10, wherein all layers of the plurality of layers that underlie an outermost layer of the plurality of layers comprise the same material. 22. A semiconductor wafer including a plurality of semiconductor device components, a protective element on selected portions of each semiconductor device component of the plurality, conductors of at least some semiconductor device components of the plurality of semiconductor device components being exposed through at least some protective elements, the protective element on one of the plurality of semiconductor device components being substantially discontinuous from protective elements on adjacent semiconductor device components and comprising a plurality of adjacent, mutually adhered regions comprising the same material. 23. The semiconductor wafer of claim 22, wherein the conductors comprise bond pads. 24. The semiconductor wafer of claim 22, wherein the protective element comprises a thermoplastic material. 25. The semiconductor wafer of claim 24, wherein the thermoplastic material comprises an adhesive. 26. The semiconductor wafer of claim 22, wherein each protective element substantially covers an active surface of a corresponding semiconductor device component of the plurality of semiconductor device components. 27. The semiconductor wafer of claim 26, wherein each protective element substantially covers an active surface of a corresponding semiconductor device component of the plurality of semiconductor device components. 28. The semiconductor wafer of claim 22, wherein at least one protective element comprises a plurality of superimposed, contiguous, mutually adhered layers. 29. The semiconductor wafer of claim 28, wherein each protective element comprises a plurality of superimposed, contiguous, mutually adhered layers. 30. The semiconductor wafer of claim 28, wherein all layers of the plurality of superimposed, contiguous, mutually adhered layers that underlie an outermost layer of the plurality of superimposed, contiguous, mutually adhered layers comprise the same material.