IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0730396
(2003-12-08)
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우선권정보 |
DE-102 57 210(2002-12-06); DE-103 19 969(2003-05-05) |
발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
7 |
초록
Multiple parallel-connected pulse-controlled inverters ( 1,2) are operated by regulating individual current(s) of the pulse-controlled inverters (1, 2) or a number reduced by 1 (n-1) of the pulse-controlled inverters (1,2).
대표청구항
▼
The invention claimed is: 1. Method of operating multiple (n) parallel-connected pulse-controlled inverters (1,2), wherein the individual current(s) of the (n) pulse-controlled inverters (1,2), or of a number reduced by 1(n-1) of pulse-controlled inverters (1,2) is/are regulated, and each pulse-con
The invention claimed is: 1. Method of operating multiple (n) parallel-connected pulse-controlled inverters (1,2), wherein the individual current(s) of the (n) pulse-controlled inverters (1,2), or of a number reduced by 1(n-1) of pulse-controlled inverters (1,2) is/are regulated, and each pulse-controlled inverter (1,2) includes first (IGBTT11, IGBTT21) and second (IGBTT14, IGBTT24) insulated gate bipolar transistors and first (D11, D21) and second (D14, D24) diodes each connected in parallel with a respective one of the first (IGBTT11, IGBTT 21) and second (IGBTT14, IGBTT24) insulated gate bipolar transistors in the direction of reverse voltage (UD-) to forward voltage (UD+), the input variable of regulation is generated by the difference between the setpoint value and the actual value of the corresponding output current, and by the modulation pattern, and for each pulse-controlled inverter (1, 2), when the actual value of current (I11, I21) is greater than the setpoint value, a turn-on edge of the first transistor (T11, T21) and turn-off edge of the second transistor (T 14, T24) are each delayed, a turn-off edge of the first transistor (T11, T21) and turn-on edge the second transistor (T14, T24) remaining undelayed, when the actual value of the current (I11, I21) is smaller than the setpoint value, the turn-on edge of the first transistor (T11, T21) and turn-off edge of the second transistor (T14, T24) are undelayed, with the turn-off edge of the first transistor (T11, T21) and turn-on edge of the second transistor (T14, T24) each being delayed, and when the actual value of the current (I11, I21) equals the setpoint value, the turn-on edges and turn-off edges of the first (T11, T21) and second (T14, T24) transistors all remain undelayed. 2. Method according to claim 1, wherein the individual currents from two pulse-controlled inverters (1, 2) are regulated. 3. Method according to claims claim 2, wherein the pulse-controlled inverters (1, 2) have the same output. 4. Method according to claim 3, wherein the total current is uniformly distributed among pulse-controlled inverters (1, 2 ) of the same output. 5. Method according to claim 2, wherein each pulse-controlled inverter (1, 2) is regulated separately, with each regulator having sensed currents to separately adjust each regulator. 6. Method according to claim 1, wherein the pulse-controlled inverters (1, 2) have the same output. 7. Method according to claim 6, wherein the total current is uniformly distributed among pulse-controlled inverters (1, 2 ) of the same output. 8. Method according to claim 7, wherein each pulse-controlled inverter (1, 2) is regulated separately, with each regulator having sensed currents to separately adjust each regulator. 9. Method according to claim 6, wherein each pulse-controlled inverter (1, 2) is regulated separately, with each regulator having sensed currents to separately adjust each regulator. 10. Method according to claim 1, wherein upon asymmetrical distribution of current, said two pulse-controlled inverters (1, 2) have setpoint/actual-value deviations of opposite polarity. 11. Method according to claim 1, wherein when the actual value of the current (I11) in one (1) of the inverters (1, 2) is excessively larger than the actual value of the current (I 21) in the other (2) of the inverters (1,2), different switching time points produce a voltage-time integral at respective output chokes (3, 6), resulting in a current change in the two chokes (3,6) in a direction of removing setpoint/actual value deviation, such that total current remains unchanged. 12. Method according to claim 1, wherein the actual values of current (I11, I21) are summed in a summing element (8 ), the resulting sum is sent to respective amplifiers (9, 10 ), where the sum is amplified by respective gain factors (K1, K 2), output of each said amplifier (9, 10) is forwarded to a respective differentiating element (11, 13) in which difference (12, 14) between the amplifier output and actual current (I11, I21) is taken, both said differences (12, 14) are then fed to a regulator (15) to which a modulation pattern (16) is also supplied, and the regulator (15) generates control pulses for the transistors (T11, T14, T21, T24). 13. Method according to claim 1 wherein each pulse-controlled inverter is regulated separately, with each regulator having sensed currents to separately adjust each regulator. 14. Method according to claim 1, wherein the control edges of the power semiconductors (T11, T14, T21, T24) are shifted within the pulse-controlled inverter(s) (1, 2). 15. Method according to claim 1, wherein each phase of one, of multiple, or of all pulse-controlled inverters (1, 2) is regulated individually. 16. Method according to claim 1, wherein the gain factors (K1, K2) of regulation are dependent on external limiting conditions.
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