IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0994568
(2001-11-26)
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우선권정보 |
KR-2001-006196(2001-02-08) |
발명자
/ 주소 |
- Cho,Yong Soo
- Park,Kyung Won
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출원인 / 주소 |
- Chung Ang University Industry Academic Cooperation Foundation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
35 인용 특허 :
6 |
초록
▼
A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system includes a radio frequency (RF) receiving module for receiving OFDM signal, an analog/digital (A/D) converter connected to the RF receiving module, the A/D converter converting the OFD
A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system includes a radio frequency (RF) receiving module for receiving OFDM signal, an analog/digital (A/D) converter connected to the RF receiving module, the A/D converter converting the OFDM signal into a digital signal, a frequency synchronization module connected to the A/D converter, the frequency synchronization module synchronizing carrier frequency, a Fast Fourier Transformer (FFT) connected to the frequency synchronization module, the FFT performing fast Fourier transformation to symbols from the frequency synchronization module, a channel estimation module connected to the FFT, the channel estimation module estimating channel response, an equalizer connected to the FFT and the channel estimation module, the equalizer equalizing channel, a residual phase tracking module connected to the equalizer, the residual phase tracking module tracking residual phase, a demodulator connected to the residual phase tracking module, the demodulator demodulating, and a controller connected to the frequency synchronization module, the controller controlling the frequency synchronization module.
대표청구항
▼
What is claimed is: 1. A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system, the frequency synchronization apparatus comprising: a radio frequency (RF) receiver for receiving an OFDM signal; an analog/digital (A/D) converter connected
What is claimed is: 1. A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system, the frequency synchronization apparatus comprising: a radio frequency (RF) receiver for receiving an OFDM signal; an analog/digital (A/D) converter connected to the RF receiver, the A/D converter converting the OFDM signal into a digital signal; a frequency synchronizer connected to the A/D converter, the frequency synchronizer synchronizing a carrier frequency; a Fast Fourier Transformer (FFT) connected to the frequency synchronizer, the FFT performing fast Fourier transformation to symbols from the frequency synchronizer; a channel estimator connected to the FFT, the channel estimator estimating a carrier channel; an equalizer connected to the FFT and the channel estimator, the equalizer configured for equalizing a channel; a residual phase tracker connected to the equalizer, the residual phase tracker configured for tracking a residual phase; a demodulator connected to the residual phase tracker, the demodulator configured for demodulating; and a controller connected to the frequency synchronizer, the controller controlling the frequency synchronizer, wherein if the received signal contains both short and long training signals, the frequency synchronizer estimates the frequency offset of the short training signal so as to compensate the long training signal with the frequency offset of the short training signal in a coarse mode, and re-estimates the frequency offset of the compensated long training signal so as to re-compensate the long training signal in a fine mode. 2. A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system, the frequency synchronization apparatus comprising: a radio frequency (RF) receiver for receiving an OFDM signal; an analog/digital (A/D) converter connected to the RF receiver, the A/D converter converting the OFDM signal into a digital signal; a frequency synchronizer connected to the A/D converter, the frequency synchronizer synchronizing a carrier frequency; a Fast Fourier Transformer (FFT) connected to the frequency synchronizer, the FFT performing fast Fourier transformation to symbols from the frequency synchronizer; a channel estimator connected to the FFT, the channel estimator estimating a carrier channel; an equalizer connected to the FFT and the channel estimator, the equalizer configured for equalizing a channel; a residual phase tracker connected to the equalizer, the residual phase tracker configured for tracking a residual phase; a demodulator connected to the residual phase tracker, the demodulator configured for demodulating; and a controller connected to the frequency synchronizer, the controller controlling the frequency synchronizer, wherein if the receiver signal contains one of both short and long training signals, the frequency synchronizer estimates frequency offset of the training signal and compensates the training signal and data symbol with the estimated frequency offset. 3. The frequency synchronization apparatus of claim 1 wherein frequency synchronizer compensates the data symbol with a sum of the frequency offsets estimated in the coarse and fine modes. 4. A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system, the frequency synchronization apparatus comprising: a radio frequency (RF) receiver for receiving an OFDM signal; an analog/digital (A/D) converter connected to the RF receiver, the A/D converter converting the OFDM signal into a digital signal; a frequency synchronizer connected to the A/D converter, the frequency synchronizer synchronizing a carrier frequency; a Fast Fourier Transformer (FFT) connected to the frequency synchronizer, the FFT performing fast Fourier transformation to symbols from the freauency synchronizer; a channel estimator connected to the FFT, the channel estimator estimating a carrier channel; an equalizer connected to the FFT and the channel estimator, the equalizer confiqured for equalizing a channel; a residual phase tracker connected to the equalizer, the residual phase tracker configured for tracking a residual phase; a demodulator connected to the residual phase tracker, the demodulator configured for demodulating; and a controller connected to the frequency synchronizer, the controller controlling the frequency synchronizer, wherein the frequency synchronizer comprises: an estimator for estimating frequency offset and residual phase of a received signal; a first demultiplexer for selectively outputting the frequency offset and residual phase estimated in the estimator; an adder for adding the frequency offsets from the first demultiplexer; a frequency offset compensator for compensating the received signal and data symbol using the frequency offsets from the first demultiplexer and the adder; and a second demultiplexer for selectively outputting a compensated signal from the frequency offset compensator. 5. The frequency synchronization apparatus of claim 4 wherein the estimator comprises: a shift register for delaying a sample of the training signal and outputting conjugate complex numbers of a predetermined training signal and a following training signal at the same time; and a selective estimator for estimating frequency offset of a signal from the shift register and residual phase of a signal from the residual phase tracker. 6. The frequency synchronization apparatus of claim 5 wherein the selective estimator comprises: a first multiplier for multiplying the conjugate complex numbers of the signal from the shift register or the residual phase tracker; a first accumulator for accumulating samples obtained by multiplication of the conjugate complex numbers at the first multiplier; a divider for generating an arctangent table address on the basis of a ratio of a real part to an imaginary part of a value accumulated at the first accumulator; an arctangent table that stores arctangent values sampled in a predetermined interval for outputting a corresponding arctangent value to the arctangent table address generated by the divider; and a phase converter for converting the arctangent value into a value of a corresponding region by referring to a sign of the accumulated value at the first accumulator and outputting the value as an estimated frequency offset. 7. The frequency synchronization apparatus of claim 6 wherein the arctangent table is configured by classifying the arctangent values into predetermined regions and storing the values in a representative one of the regions as representative values. 8. The frequency synchronization apparatus of claim 4 wherein the frequency offset compensator comprises: a bit expander for sampling the estimated frequency offset; a second accumulator for generating a first log function table address by accumulating frequency offset of each sample obtained at the bit expander; a first region controller for converting the first log function table address into a corresponding address value in a predetermined region by referring to a sign of value at the bit expander; a first log function table for outputting a previously stored log function value according to the address value from the first region controller; and a second multiplier for compensating frequency offset by multiplying the training signal or the data symbol by the log function value from the first log function table. 9. The frequency synchronization apparatus of claim 8 wherein the first log function table is configured by dividing sine and cosine values into predetermined regions and storing values in one of the regions as representative values corresponding to the values in the other regions. 10. The frequency synchronization apparatus of claim 9 wherein the first region controller outputs an address value resulting from a subtraction of a predetermined value from an output value and then shifts the present region to a next region if the output value is greater than the predetermined value. 11. The frequency synchronization apparatus of claim 9, wherein the first region controller performs a complementary operation with the output value of the second accumulator for obtaining a sine or cosine value in the representative regions. 12. A freguency synchronization apparatus for an orthogonal freguency division multiplexing (OFDM) communication system, the freguency synchronization apparatus comprising: a radio freauency (RF) receiver for receiving an OFDM signal; an analog/digital (A/D) converter connected to the RF receiver, the A/D converter converting the OFDM signal into a digital signal; a freguency synchronizer connected to the A/D converter, the freguency synchronizer synchronizing a carrier freguency; a Fast Fourier Transformer (FFT) connected to the freguency synchronizer, the FFT performing fast Fourier transformation to symbols from the freguency synchronizer; a channel estimator connected to the FFT, the channel estimator estimating a carrier channel; an egualizer connected to the FFT and the channel estimator, the egualizer configured for egualizing a channel; a residual phase tracker connected to the equalizer, the residual phase tracker configured for tracking a residual phase; a demodulator connected to the residual phase tracker, the demodulator configured for demodulating; and a controller connected to the frequency synchronizer, the controller controlling the frequency synchronizer, wherein the residual phase tracker comprises: a pilot extractor for extracting a pilot signal from a data symbol transformed by the FFT and sending the pilot signal to the frequency synchronizer; a residual phase compensator for compensating the data symbol with the residual phase of the data symbol estimated at the frequency synchronizer. 13. The frequency synchronization apparatus of claim 12 wherein the residual phase compensator comprises: a second region controller for outputting a second log function table address corresponding to the residual phase value from the first demultiplexer; a second log function table for outputting a previously stored log function value corresponding to the log function table address from the second region controller; and a third multiplier for compensating the residual phase by multiplying the log function value from the second log function table with the compensated data symbol. 14. The frequency synchronization apparatus of claim 13 wherein the second log function table is configured by dividing sine and cosine values into predetermined regions and values in one of the regions are stored as representative values corresponding to the values in the other regions. 15. The frequency synchronization apparatus of claim 14 wherein the second region controller outputs an address value resulting from a subtraction of a predetermined value from an output value and then shifts the present region to a next region if the output value is greater than the predetermined value. 16. The frequency synchronization apparatus of claim 15 wherein the second region controller performs a complementary operation with the output value of the second accumulator for obtaining a sine or cosine value in the representative region. 17. A frequency synchronization method for an orthogonal frequency division multiplexing (OFDM) communication system comprising: estimating a frequency offset of a training signal; compensating a frequency of the training signal with the estimated frequency offset; performing fast Fourier transformation on the frequency; compensating a data symbol of an input signal with the estimated frequency offset; performing fast Fourier transformation on the data symbol; compensating the data symbol with the estimated channel obtained by performing the fast Fourier transformation; tracking a residual phase of the estimated data symbol; and compensating the residual phase. 18. The frequency synchronization method of claim 17 wherein the estimating of the frequency offset, if the training signal has short and long training signals, comprises: estimating the frequency offset using the short training signal; compensating the long training signal with the estimated frequency offset of the short training in a coarse mode; estimating a frequency offset of the long compensated training signal; and re-compensating the compensated long training signal with the estimated frequency offset in a fine mode. 19. A frequency synchronization method of claim 18 wherein the data symbol is compensated with a sum of the frequency offsets estimated in the fine and coarse modes. 20. The frequency synchronization method of claim 18 wherein the estimating of the frequency offset using the short training signal, comprises: delaying a sample of the short training signal; outputting conjugate complex numbers of a present training signal and a following training signal at the same time; multiplying the conjugate complex numbers of the short training signal; accumulating values of the samples obtained by the multiplying; first generating an arctangent table address on the basis of a ratio of a real and imaginary parts of the accumulated values; referring to a sign of the accumulated value; converting an arctangent value stored in the first generated arctangent table address of a generated arctangent table into a value in a corresponding region; and outputting the value as an estimated frequency offset. 21. The frequency synchronization method of claim 20 wherein compensating the lone training signal with the estimated freguency offset of the short training in a coarse mode comprises: sampling the estimated frequency offset in a predetermined size; accumulating values of samples; generating a first log function table address on the basis of the accumulated value; referring to a sign of the accumulated value; converting a first log function table address into an address in a corresponding region; and first outputting a log function stored at the converted address. 22. The frequency synchronization method of claim 21 wherein the first output log function value is multiplied with the long training signal. 23. The frequency synchronization method of claim 20 wherein the first generated arctangent table is configured by classifying the arctangent values into predetermined regions and storing the values in a representative one of the regions as representatives. 24. The frequency synchronization method of claim 21 wherein the log function value is outputted after a complementary operation for obtaining a sine or cosine value in symmetrical regions. 25. The frequency synchronization method of claim 21 wherein the first log function table is configured such that dividing sine and cosine values into predetermined regions and values in one of the regions are stored as representative values corresponding to the values in the other regions. 26. The frequency synchronization method of claim 21 wherein an address value resulting from a subtraction of a predetermined value from an output value is outputted and then the present region is shifted to a next region if the output value is greater than the predetermined value. 27. The frequency synchronization method of claim 21 wherein estimating a freguency offset of the long compensated training signal comprises: delaying a sample of the compensated long training signal; outputting conjugate complex numbers of a present long training signal and a following training signal at the same time; multiplying the conjugate complex numbers of the long training signal; accumulating values of samples obtained by multiplication of the conjugate complex numbers of the long training signal; second generating an arctangent table address on the basis of a ratio of real and imaginary parts of the accumulated value obtained by multiplication of the conjugate complex numbers of the long training signal; referring to a sign of the accumulated value; converting the arctangent value stored in the second generated arctangent table address of an arctangent table into a value in a corresponding region; and outputting the value as an estimated frequency offset. 28. The frequency synchronization method of claim 27 wherein the re-compensating comprises: sampling the estimated frequency offset in a predetermined size; accumulating values of samples; generating a log function table address on the basis of the accumulated value; referring to a sign of the accumulated value; converting a first log function table address of a first log function table into an address in a corresponding region; and second outputting a log function value stored at the converted address. 29. The frequency synchronization method of claim 28 wherein the second output log function value is multiplied with the long training signal. 30. The frequency synchronization method of claim 27 wherein the arctangent table is configured classifying the arctangent values into predetermined regions and storing the values in a representative one of the regions as representatives. 31. The frequency synchronization method of claim 28 wherein the log function value is outputted after a complementary operation for obtaining a sine or cosine value in symmetrical regions. 32. The frequency synchronization method of claim 28 wherein the first log function table is configured such that dividing sine and cosine values into predetermined regions and values in one of the regions are stored as representative values corresponding to the values in the other regions. 33. The frequency synchronization method of claim 28 wherein an address value resulting from a subtraction of a predetermined value from an output value is outputted and then the present region is shifted to a next region if the output value is greater than the predetermined value. 34. The frequency synchronization method of claim 17 wherein tracking a residual phase comprises: extracting a pilot signal from the compensated data symbol; performing a conjugate complex number multiplication; accumulating values of samples obtained by the complex number multiplication; generating an aretangent table address on the basis of a ratio of real and imaginary parts of the accumulated value; referring to a sign of the accumulated value; converting the arctangent value stored in the generated arctangent table address of an arctangent table into a value in a corresponding region; outputting the value as an estimated residual phase; generating a second log function table address according to the estimated residual phase; outputting a log function value corresponding to the second log function table address of a second log function table; and multiplying the log function value with the data symbol. 35. The frequency synchronization method of claim 34 further comprising classifying the arctangent values into predetermined regions and storing the values in a representative one of the regions as representative values. 36. The frequency synchronization method of claim 34 the second log function table further comprising dividing sine and cosine values into predetermined regions and storing values in one of the regions as representative values corresponding to the values in the other regions. 37. The frequency synchronization method of claim 34 further comprising outputting an address value resulting from a subtraction of a predetermined value from an output value and shifting the present region to a next region if the output value is greater than the predetermined value. 38. The frequency synchronization method of claim 34 further comprising outputting sine and cosine values after performing a complementary operation with the log function value for obtaining sine or cosine value in symmetrical regions.
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