초록 ▼

Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a translation lookaside buffer (TLB) that caches mappings to speed translation of virtual addresses. Each

Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a translation lookaside buffer (TLB) that caches mappings to speed translation of virtual addresses. Each processor also maintains a counter. Each time a processor's TLB is flushed, the processor's counter is incremented. When a link to a page is removed from an address translation map, the counter values for all of the processors are recorded. When that page is accessed by a processor, the recorded counter values are compared with the processor's current counter value to determine whether the processor's TLB has been flushed since the link to the page was removed from the map. An expensive TLB flush operation is delayed until needed, but still occurs early enough to prevent an invalid TLB entry from being used to violate the access policy.

대표청구항 ▼

What is claimed: 1. A method of clearing obsolete entries from a first one of a plurality of mapping caches, each of the plurality of mapping caches being associated with a corresponding one of a plurality of processing units of a computing device, each of the caches being used to translate virtual

What is claimed: 1. A method of clearing obsolete entries from a first one of a plurality of mapping caches, each of the plurality of mapping caches being associated with a corresponding one of a plurality of processing units of a computing device, each of the caches being used to translate virtual addresses to physical addresses and storing mappings based on an address translation map, the method comprising: maintaining a counter; updating said counter each time the first one of the plurality of mapping caches is flushed; recording said counter's value in response to a change in the address translation map, whereby a recorded counter value is stored; determining, based on a comparison of said counter's value with the recorded counter value, that the first one of the plurality of mapping caches has not definitely been flushed since said change in the address translation map occurred; and flushing the first one of the plurality of mapping caches; wherein a policy defines permissible access to a memory, and wherein the method further comprises: controlling the content of the address translation map such that the address translation map does not expose to an entity virtual address mappings that would permit said entity to access said memory in violation of said policy; wherein said change comprises either a modification to the map that places or maintains the map in conformance with said policy, or a modification to the map that limits said entity's write access to the map. 2. The method of claim 1, wherein the address translation map comprises a link to a portion of said memory, wherein controlling the content of the address translation map comprises making said portion of said memory inaccessible to said entity, and wherein said change comprises removing all links to said portion of said memory from the address translation map. 3. A system for managing the use of address mapping caches, the system comprising: a plurality of processors, each of the processors having a mapping cache and a counter associated therewith; a memory that stores an address translation map, each of the mapping caches storing mappings based on said address translation map, there being a policy that governs access to said memory, the contents of the address translation map being controlled to prevent exposure of mappings that permit access to said memory in violation of said policy; first logic that flushes a first one of the mapping caches and that increments a first one of the counters when said first one of the mapping caches is flushed; second logic that records the value of said first counter in response to a change in said address translation map or in a property regarding said address translation map, the recorded counter value being stored in association with said change; third logic that compares the recorded counter value with the value of the first counter and that causes said first one of the mapping caches to be flushed if the comparison indicates that said first one of the mapping caches has not been flushed since the change. 4. The system of claim 3, wherein each of the processors is associated with said first one of the counters, and wherein said first logic increments said first one of the counters when any of the mapping caches is flushed. 5. The system of claim 3, wherein each of the mapping caches is associated with a different one of a plurality of counters, and wherein said first logic increments the counter corresponding to a given mapping cache when the given mapping cache is flushed. 6. The system of claim 3, wherein said change comprises placing said address translation map in a state in which all links to a first page of said memory are removed from said address translation map. 7. The system of claim 3, wherein said change comprises placing said address translation map in a state in which there is no writeable link to a first page of said memory. 8. The system of claim 3, wherein said third logic is invoked in response to a detection that a result of said change is to be used. 9. The system of claim 8, wherein said change comprises placing said address translation map in a state in which all links to a first page of said memory are removed from said address translation map, and wherein said detection is based on a virtual address having been translated to a location on said first page.