초록 ▼

A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centraliz

A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.

대표청구항 ▼

What is claimed is: 1. A programmable logic device (PLD), comprising: a plurality of complex programmable logic device (CPLD) function blocks disposed to implement a two-dimensional array of the CPLD function blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at

What is claimed is: 1. A programmable logic device (PLD), comprising: a plurality of complex programmable logic device (CPLD) function blocks disposed to implement a two-dimensional array of the CPLD function blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure; a plurality of input/output (I/O) blocks; a plurality of segmented interconnect lines; a plurality of first programmable multiplexer circuits programmably coupling the CPLD function blocks to the segmented interconnect lines; a plurality of second programmable multiplexer circuits programmably coupling the I/O blocks to the segmented interconnect lines; and a plurality of programmable switch matrices programmably coupling the segmented interconnect lines one to another. 2. The PLD of claim 1, wherein the array includes at least three rows and three columns of the CPLD function blocks. 3. The PLD of claim 1, wherein the segmented interconnect lines comprise interconnect lines having different lengths. 4. The PLD of claim 3, wherein the segmented interconnect lines comprise interconnect lines spanning different numbers of the CPLD function blocks. 5. The PLD of claim 1, wherein the segmented interconnect lines comprise a plurality of horizontal interconnect lines and a plurality of vertical interconnect lines. 6. The PLD of claim 5, wherein the programmable switch matrices programmably couple the horizontal interconnect lines to the vertical interconnect lines. 7. The PLD of claim 5, wherein the programmable switch matrices programmably couple the horizontal interconnect lines one to another and further programmably couple the vertical interconnect lines one to another. 8. A programmable logic device (PLD), comprising: a plurality of complex programmable logic device (CPLD) function blocks disposed to implement a two-dimensional array comprising rows and columns of the CPLD function blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure; a plurality of first segmented interconnect lines disposed between adjacent rows of the CPLD function blocks; a plurality of second segmented interconnect lines disposed between adjacent columns of the CPLD function blocks; and a plurality of first programmable multiplexer circuits programmably coupling the CPLD function blocks to the first and second segmented interconnect lines. 9. The PLD of claim 8, further comprising: a plurality of input/output (I/O) blocks; and a plurality of second programmable multiplexer circuits programmably coupling the I/O blocks to the first and second segmented interconnect lines. 10. The PLD of claim 8, wherein the array includes at least three rows and three columns of the CPLD function blocks. 11. The PLD of claim 8, further comprising a plurality of programmable switch matrices programmably coupling the first segmented interconnect lines to the second segmented interconnect lines. 12. The PLD of claim 11, wherein the programmable switch matrices further programmably couple the first segmented interconnect lines one to another, and further programmably couple the second segmented interconnect lines one to another. 13. The PLD of claim 8, wherein each of the first and second segmented interconnect lines comprises interconnect lines having different lengths. 14. The PLD of claim 13, wherein each of the first and second segmented interconnect lines comprises interconnect lines spanning different numbers of the CPLD function blocks. 15. A programmable logic device (PLD), comprising: a two-dimensional array comprising rows and columns of complex programmable logic device (CPLD) function blocks and input/output (I/O) blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure; a programmable interconnect structure disposed between each pair of adjacent rows and each pair of adjacent columns in the array, the programmable interconnect structure comprising a plurality of segmented interconnect lines; and a plurality of programmable multiplexer circuits programmably coupling the CPLD function blocks and the I/O blocks to the programmable interconnect structure. 16. The PLD of claim 15, wherein the plurality of programmable multiplexer circuits comprises: a plurality of first programmable multiplexer circuits programmably coupling the CPLD function blocks to the programmable interconnect structure; and a plurality of second programmable multiplexer circuits programmably coupling the I/O blocks to the programmable interconnect structure. 17. The PLD of claim 15, wherein the array includes at least three rows and three columns of the CPLD function blocks. 18. The PLD of claim 15, wherein the programmable interconnect structure further comprises a plurality of programmable switch matrices programmably coupling the segmented interconnect lines one to another. 19. The PLD of claim 15, wherein the programmable interconnect structure further comprises segmented interconnect lines having different lengths. 20. The PLD of claim 19, wherein the segmented interconnect lines comprise interconnect lines spanning different numbers of the CPLD function blocks. 21. The PLD of claim 15, wherein the CPLD function blocks are implemented within an interior portion of the array, and the I/O blocks are implemented in a ring around the interior portion.