초록 ▼

A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the

A semiconductor device and fabrication thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

대표청구항 ▼

What is claimed is: 1. A semiconductor device, comprising: a substrate; at least one transistor on the substrate; a first dielectric layer on the transistor and having an opening exposing an active region of the transistor; an atomic layer deposited (ALD) TaN barrier conformably lining the opening,

What is claimed is: 1. A semiconductor device, comprising: a substrate; at least one transistor on the substrate; a first dielectric layer on the transistor and having an opening exposing an active region of the transistor; an atomic layer deposited (ALD) TaN barrier conformably lining the opening, at a thickness less than 20 Å; and a copper layer over the atomic layer deposited (ALD) TaN barrier, filling the opening. 2. The semiconductor device of claim 1, wherein first dielectric layer comprises phosphorous-containing dielectric. 3. The semiconductor device of claim 2, wherein the phosphorous-containing dielectric is phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). 4. The semiconductor device of claim 1, wherein the active region is a source/drain region of the transistor. 5. The semiconductor device of claim 1, wherein the active region is a gate electrode of the transistor. 6. The semiconductor device of claim 1, further comprising a copper seed layer between the copper layer and the atomic layer deposited (ALD) TaN barrier. 7. A semiconductor device, comprising: a substrate; at least one transistor on the substrate; a first dielectric layer covering the transistor and having an first opening exposing an active region of the transistor; a first atomic layer deposited (ALD) TaN barrier conformably lining the first opening, at a thickness less than 20 Å; a first copper layer over the first atomic layer deposited (ALD) TaN barrier, filling the first opening; a second dielectric layer over the first dielectric layer and having a second opening that exposes a portion of the first copper layer; a second atomic layer deposited (ALD) TaN barrier conformably lining the second opening, at a thickness less than 20 Å; and a second copper layer over the second ALD TaN barrier layer, filling the second opening. 8. The semiconductor device of claim 7, wherein the second dielectric layer comprises phosphorous-containing dielectric. 9. The semiconductor device of claim 8, wherein the phosphorous-containing dielectric is phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).