Electrical interconnection, method of forming the electrical interconnection, image sensor having the electrical interconnection and method of manufacturing the image sensor
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/4763
H01L-021/02
H01L-021/44
출원번호
US-0879076
(2004-06-30)
우선권정보
KR-10-2003-0044099(2003-07-01)
발명자
/ 주소
Won,Seok Jun
출원인 / 주소
Samsung Electronics Co., Ltd.
대리인 / 주소
Lee &
인용정보
피인용 횟수 :
14인용 특허 :
5
초록▼
An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of h
An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.
대표청구항▼
What is claimed is: 1. A method of forming an electrical interconnection, comprising: forming a first insulation layer on a semiconductor substrate; forming at least a first recessed portion in the first insulation layer; filling the first recessed portion with metal to form a first metal pattern;
What is claimed is: 1. A method of forming an electrical interconnection, comprising: forming a first insulation layer on a semiconductor substrate; forming at least a first recessed portion in the first insulation layer; filling the first recessed portion with metal to form a first metal pattern; forming a metal anti-oxidation layer on the first insulation layer and the first metal pattern, the metal anti-oxidation layer preventing the first metal pattern from being oxidized; forming a first diffusion barrier layer on the metal anti-oxidation layer, the first metal pattern and the first insulation layer, the first diffusion barrier layer including a metal oxide and preventing metal of the first metal pattern from diffusing out of the first metal pattern; forming a second insulation layer on the first diffusion barrier layer; forming at least a second recessed portion in the second insulation layer, the second recessed portion exposing a portion of the first metal pattern; and filling the second recessed portion with metal to form a second metal pattern, wherein the metal anti-oxidation layer is formed before the first diffusion barrier layer to be under the first diffusion barrier layer. 2. The method of forming an electrical interconnection as claimed in 1, wherein the first diffusion barrier layer is formed by depositing aluminum oxide. 3. The method of forming an electrical interconnection as claimed in claim 2, wherein the aluminum oxide is deposited by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) or a Sol-Gel process. 4. The method of forming an electrical interconnection as claimed in claim 1, wherein forming a second insulation layer comprises: forming a lower layer on the first diffusion barrier layer; forming an etching stop layer for stopping an etching process on the lower layer; and forming an upper layer on the etching stop layer. 5. The method of forming an electrical interconnection as claimed in claim 4, wherein forming a second recessed portion comprises: selectively removing the upper layer, the etching stop layer and the lower layer, thereby forming a space surrounded by the upper layer, the etching stop layer and the lower layer and exposing a portion of the first diffusion barrier layer; removing the upper layer neighboring the space, thereby exposing a portion of the etching stop layer; and removing the exposed etching stop layer and the first diffusion barrier layer, thereby exposing the first metal pattern. 6. The method of forming an electrical interconnection as claimed in claim 5, wherein forming the second metal pattern comprises: depositing metal on the upper layer to a predetermined thickness, thereby filling the second recessed portion with metal and forming a metal layer; and planarizing the metal layer, thereby exposing a surface of the upper layer. 7. The method of forming an electrical interconnection as claimed in claim 6, wherein forming the second insulation layer, forming the second recessed portion and forming the second metal pattern are sequentially repeated, thereby forming a plurality of the second insulation layers vertically stacked thereon and a plurality of the second metal patterns disposed in each of the second insulation layers. 8. The method of forming an electrical interconnection as claimed in claim 7, further comprising forming at least a second diffusion barrier layer on a boundary region of the second insulation layers, the second diffusion barrier for layer preventing metal from diffusing from the second metal pattern. 9. The method of forming an electrical interconnection as claimed in claim 8, wherein the second diffusion layer is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) or a Sol-Gel process. 10. The method of forming an electrical interconnection as claimed in claim 9, further comprising forming another metal anti-oxidation layer under the second diffusion barrier layer, the another metal anti-oxidation layer preventing the second metal pattern from being oxidized. 11. The method of forming an electrical interconnection as claimed in claim 4, wherein forming the etching stop layer includes depositing aluminum oxide on the lower layer. 12. A method of manufacturing an image device, comprising: forming a semiconductor device including an optoelectronic device on the semiconductor substrate; forming a lower insulation layer including a first metal pattern on the semiconductor substrate, the first metal pattern being electrically connected with the semiconductor device; forming a lower diffusion barrier layer on the lower insulation layer, the lower diffusion barrier layer including metal oxide and preventing metal of the first metal pattern from diffusing out of the first metal pattern; forming at least an insulating interlayer on the lower insulation layer, the insulating interlayer including at least a recessed portion; filling the recessed portion with metal, thereby forming a second metal pattern; forming a metal anti-oxidation layer on the insulating interlayer and the second metal pattern, the metal anti-oxidation layer preventing the second metal pattern from being oxidized; forming an upper diffusion barrier layer on the metal anti-oxidation layer, the second metal pattern and the insulating interlayer, the upper diffusion barrier layer including a metal oxide and preventing metal of the second metal pattern from diffusing out of the second metal pattern; forming a color filter on the upper diffusion barrier layer; and forming a lens on the color filter, wherein the metal anti-oxidation layer is formed before the first diffusion barrier layer to be under the upper diffusion barrier layer. 13. The method of manufacturing an image device as claimed in claim 12, wherein forming the insulating interlayer includes forming a lower layer having at least a via-hole for exposing the first metal pattern and forming an upper layer having at least a trench connected to the via-hole, and wherein forming the second metal pattern includes forming a via contact including copper along the via-hole and forming a trench contact including copper along the trench. 14. The method of manufacturing an image device as claimed in claim 13, wherein forming the insulating interlayer and forming the second metal pattern are alternatively repeated, so that a plurality of the insulating interlayers is stacked on the lower diffusion barrier layer, each of the plurality of insulating interlayers including a corresponding one of the second metal pattern, the second metal patterns being electrically connected with each other in an order stacked by electrically connecting trench contacts and adjacent via contacts. 15. The method of manufacturing an image device as claimed in claim 14, further comprising forming at least a middle diffusion barrier layer including a metal oxide between at least one of the insulating interlayers and the corresponding, second metal pattern, the middle diffusion barrier layer preventing diffusion of copper from the trench contact. 16. The method of manufacturing an image device as claimed in claim 15, wherein the upper, lower and middle diffusion layers are formed by depositing aluminum oxide. 17. The method of manufacturing an image device as claimed in claim 16, wherein the aluminum oxide is deposited by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) or a Sol-Gel process. 18. The method of manufacturing an image device as claimed in claim 15, further comprising forming an anti-oxidation layer before forming the middle diffusion barrier layer, the anti-oxidation layer preventing the trench contact from being oxidized. 19. The method of manufacturing an image device as claimed in claim 13, further comprising forming an etching stop layer between the lower layer and the upper layer, the etching stop layer being used for stopping an etching process for forming the trench. 20. The method of manufacturing an image device as claimed in claim 19, wherein the etching stop layer is formed by depositing aluminum oxide on the lower layer.
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