Microelectromechanical device and method for producing it
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-021/00
H01L-021/76
H01L-021/70
출원번호
US-0773114
(2004-02-04)
우선권정보
DE-103 05 411(2003-06-02)
발명자
/ 주소
B철ttner,Harald
Schubert,Axel
Nurnus,Joachim
Jagle,Martin
출원인 / 주소
Infineon Technologies AG
Fraunhofer Gesellschaft zur Forde rung der angewandten Forschung e. V.
대리인 / 주소
Dickstein, Shapiro, Morin &
인용정보
피인용 횟수 :
13인용 특허 :
2
초록▼
A microelectromechanical device and a method for producing it having at least one layer on a substrate, in particular a thermoelectric layer on a substrate, the thermal expansion coefficient of the at least one layer and the thermal expansion coefficient of the substrate differing greatly. The at le
A microelectromechanical device and a method for producing it having at least one layer on a substrate, in particular a thermoelectric layer on a substrate, the thermal expansion coefficient of the at least one layer and the thermal expansion coefficient of the substrate differing greatly. The at least one layer is coupled to at least one stress reduction means for the targeted reduction of lateral mechanical stresses present in the layer. This achieves a stress-free layer or enables stress-free growth.
대표청구항▼
The invention claimed is: 1. A microelectromechanical device comprising at least one thermoelectric layer on a substrate, wherein a thermal expansion coefficient of said at least one thermoelectric layer differs greatly from a thermal expansion coefficient of the substrate, wherein said at least on
The invention claimed is: 1. A microelectromechanical device comprising at least one thermoelectric layer on a substrate, wherein a thermal expansion coefficient of said at least one thermoelectric layer differs greatly from a thermal expansion coefficient of the substrate, wherein said at least one thermoelectric layer is coupled to at least one stress reduction means for the targeted reduction of lateral mechanical stresses present in the layer, wherein at least one stress reduction means is arranged between regions of at least one of a functional structure and a region with a thermoelectric layer, and wherein the stress reduction means comprises at least one of: (a) an antiadhesion layer for reducing or preventing the adhesion of material of the layer and thus for forming at least one stress reduction means, (b) a vertical offset between two laterally adjoining layers is arranged as said stress reduction means in at least one region on the substrate, and (c) at least one trench is arranged as said stress reduction means in at least one region of the substrate. 2. The microelectromechanical device as claimed in claim 1, wherein the antiadhesion layer comprises at least one of Ti--W alloy and SiO2. 3. The microelectromechanical device as claimed in claim 1, wherein the vertical offset is formed by a prestructuring of the substrate using at least one of an electrode metal and an adhesion layer. 4. The microelectromechanical device as claimed in claim 1, wherein at least one trench has a depth of up to 100 μm. 5. The microelectromechanical device as claimed in claim 1, wherein the substrate comprises at least one of mica, glass, BaF2 , silicon, silicon dioxide, silicon carbide and diamond. 6. The microelectromechanical device as claimed in claim 1, wherein said thermoelectric layer forms at least one of a Peltier element and a thermogenerator element. 7. The microelectromechanical device as claimed in claim 1, wherein the thermoelectric layer comprises a thermoelectric material including at least one of Bi2Te3, PbTe, SiGe and skutterrudite. 8. The microelectromechanical device as claimed in claim 1, wherein the difference between the thermal expansion coefficient of at least one layer and the thermal expansion coefficient of the substrate is at least 3*10-6 K-1. 9. The microelectromechanical device as claimed in claim 8, wherein the difference between the thermal expansion coefficient of at least one layer and the thermal expansion coefficient of the substrate is at least 10-5 K-1. 10. The microelectromechanical device as claimed in claim 1, wherein the layer thickness of said thermoelectric layer is in the range of 2 and 100 μm. 11. The microelectromechanical device as claimed in claim 10, wherein the layer thickness is in the range of 20 and 100 μm. 12. A method for producing a thermoelectric semiconductor component, the method comprising forming a layer on a substrate such that the layer is coupled to at least one stress reduction means for the targeted reduction of lateral mechanical stresses present in the layer, wherein forming the layer comprises forming a thermoelectric layer, and wherein the method further comprises arranging said at least one stress reduction means between regions of at least one of a functional structure and a region with a thermoelectric layer, and wherein forming the stress reduction means comprises at least one of: (a) forming an antiadhesion layer for reducing or preventing the adhesion of material of the layer and thus for forming at least one stress reduction means in at least one region of the substrate, (b) arranging a vertical offset between two laterally adjoining layers as said stress reduction means in at least one region on the substrate, and (c) producing at least one trench using at least one of mechanical and chemical processes as said stress reduction means in at least one region of the substrate. 13. A microelectromechanical device comprising: a substrate having a first thermal expansion coefficient; and a thermoelectric layer formed over the substrate, the thermoelectric layer having a second thermal expansion coefficient that differs from the first thermal expansion coefficient by at least 10-5 K-1; wherein said at least one thermoelectric layer is divided into a plurality of thermoelectric layer portions, each thermoelectric layer portion being separated from adjacent thermoelectric layer portions by a stress reduction region, and wherein said each thermoelectric layer portion has a thickness in the range of 2 and 100 μm, and a width in the range of 1. 4 to 20 mm, and wherein each stress reduction region comprises at least one of: (a) an antiadhesion layer for reducing or preventing the adhesion of material of the layer and thus for forming at least one stress reduction means, (b) a vertical offset between two laterally adjoining layers is arranged as said stress reduction means in at least one region on the substrate, and (c) at least one trench is arranged as said stress reduction means in at least one region of the substrate.
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이 특허에 인용된 특허 (2)
Shuzo Sudo JP; Matsuo Kishi JP; Hirohiko Nemoto JP, Thermoelectric conversion device and method of manufacturing the same.
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