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A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current i

A band-gap reference circuit for generation of voltages and currents independent of process, voltage, and temperature includes three inversely proportional to absolute temperature (IPTAT) current generators. The IPTAT current generators generate three currents that are added to generate a current independent of the absolute temperature. The generated current is passed through a switched capacitor resistor to generate the band-gap reference voltage across the switched capacitor resistor.

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The invention claimed is: 1. A band-gap reference circuit that generates a band-gap reference voltage, the band-gap reference circuit comprising: a first inversely proportional to absolute temperature (IPTAT) current generator that generates a first current; a second IPTAT current generator, connec

The invention claimed is: 1. A band-gap reference circuit that generates a band-gap reference voltage, the band-gap reference circuit comprising: a first inversely proportional to absolute temperature (IPTAT) current generator that generates a first current; a second IPTAT current generator, connected in parallel with the first IPTAT current generator, that generates a second current; a third IPTAT current generator, connected in series with the first IPTAT current generator, that generates a third current; and a resistor, connected in series with the first and second IPTAT current generators and in parallel with the third IPTAT generator, wherein the band-gap reference voltage is generated across the resistor, wherein each of the first, second, and third IPTAT current generators comprises: a first PMOS transistor having a source connected to a supply voltage, a drain and a gate; a second PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the first PMOS transistor at a PBIAS node, and a drain; a third PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the second PMOS transistor at the PBIAS node, and a drain from which the current generated by the IPTAT is drawn; a third capacitor having a first terminal connected to the supply voltage, and a second terminal connected to the gate of the third PMOS transistor; a PNP transistor having an emitter connected to the drain of the first PMOS transistor, a base connected to a reference voltage, and a collector connected to the reference voltage; a comparator circuit having a first input coupled to the emitter of the PNP transistor, a second input coupled to the drain of the second PMOS transistor, and an output connected to the gates of the first and second PMOS transistors at the PBIAS node, the output providing a bias voltage to the first, second, and third PMOS transistors; a fourth capacitor having a first terminal connected to the emitter of the PNP transistor, and a second terminal connected to the reference voltage; a fifth capacitor having a first terminal connected to the drain of the second PMOS transistor, and a second terminal connected to the reference voltage; and a switched capacitor resistor having a first node connected to the drain of the second PMOS transistor, and a second node connected to the reference voltage. 2. The band-gap reference circuit of claim 1, wherein an output current that passes through the resistor comprises the first current and a difference between the second and third currents. 3. The band-gap reference circuit of claim 1, wherein the resistor comprises a switched capacitor resistor. 4. The band-gap reference circuit of claim 3, wherein the switched capacitor resistor comprises: a first NMOS transistor having a drain connected to a first node at a voltage VCAP, a gate connected to a first clock signal, and a source, the first node receiving the output current; a second NMOS transistor having a drain connected to the first node, a gate connected to a second clock signal, and a source; a third NMOS transistor having a drain connected to the source of the first NMOS transistor, a gate connected to the second clock signal, and a source connected to a reference voltage; a fourth NMOS transistor having a drain connected to the source of the second NMOS transistor, a gate connected to the first clock signal, and a source connected to the reference voltage; a first capacitor having a first terminal connected to the source of the first NMOS transistor, and a second terminal connected to the reference voltage; and a second capacitor having a first terminal connected to the source of the second NMOS transistor, and a second terminal connected to the reference voltage. 5. The band-gap reference circuit of claim 4, wherein the first clock and the second clock signals are non-overlapping clock signals. 6. The band-gap reference circuit of claim 1, wherein the switched capacitor resistor comprises: a first NMOS transistor having a drain connected to a first node at a voltage VCAP, a gate connected to a first clock signal, and a source, the first node receiving the output current; a second NMOS transistor having a drain connected to the first node, a gate connected to a second clock signal, and a source; a third NMOS transistor having a drain connected to the source of the first NMOS transistor, a gate connected to the second clock signal, and a source connected to a reference voltage; a fourth NMOS transistor having a drain connected to the source of the second NMOS transistor, a gate connected to the first clock signal, and a source connected to the reference voltage; a first capacitor having a first terminal connected to the source of the first NMOS transistor, and a second terminal connected to the reference voltage; and a second capacitor having a first terminal connected to the source of the second NMOS transistor, and a second terminal connected to the reference voltage. 7. A band-gap reference circuit that generates a band-gap reference voltage the band-gap circuit comprising: a first switched capacitor resistor having a first node at which the band-gap reference voltage is generated, and a second node connected to a reference voltage; a first inversely proportional to absolute temperature (IPTAT) current generator having a first bias voltage at a first PBIAS node, and a first output node connected to the first node of the first switched capacitor, wherein a first output current generated by the first IPTAT current generator is drawn from the first output node; a second IPTAT current generator having a second bias voltage at a second PBIAS node, and a second output node, wherein a second output current generated by the second IPTAT current generator is drawn from the second output node; a first capacitor having a first terminal connected to the first output node, and a second terminal connected to the reference voltage; a PMOS transistor having a source connected supply voltage, a gate connected to the first PBIAS node, and a drain connected to the first terminal of the first capacitor; a first NMOS transistor having a drain connected to connected to the drain of the PMOS transistor, a source connected to the reference voltage, and a gate; and a second NMOS transistor having a gate connected to the gate of the first NMOS transistor, a source connected to the reference voltage, and a drain connected to the second output node and to the gate of the first NMOS transistor, wherein the first IPTAT current generator comprises: a first PMOS transistor having a source connected to the supply voltage, a gate connected to the first PBIAS node, and a drain; a second PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the first PMOS transistor and a drain; a third PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the second PMOS transistor, and a drain connected to the first output node; a fourth capacitor having a first terminal connected to the supply voltage, and a second terminal connected to the gate of the third PMOS transistor; a first PNP transistor having an emitter connected to a drain of the first PMOS transistor, a base connected to the reference voltage, and a collector connected to the reference voltage: a first comparator circuit having an input coupled to the emitter of the first PNP transistor, second input coupled to the drain of the second PMOS transistor, and an output connected to the gates of the first and second PMOS transistors; a fifth capacitor having a first terminal connected to the emitter of the first PNP transistor, and a second terminal connected to the reference voltage; and a sixth capacitor having a first terminal connected to a drain of the second PMOS transistor, and a second terminal connected to the reference voltage; and a second switched capacitor resistor having a first node connected to the drain of the second PMOS transistor, and a second node connected to the reference voltage. 8. The band-gap reference circuit of claim 7, wherein the first switched capacitor resistor comprises: a third NMOS transistor having a drain connected to the first node, a gate connected to a first clock signal, and a source; a fourth NMOS transistor having a drain connected to the first node, a gate connected to a second clock signal, and a source; a fifth NMOS transistor having a drain connected to the source of the third NMOS transistor, a gate connected to the second clock signal, and a source connected to the reference voltage; a sixth NMOS transistor having a drain connected to the source of the fourth NMOS transistor, a gate connected to the first clock signal, and a source connected to the reference voltage; a second capacitor having a first terminal connected to the source of the third NMOS transistor, and a second terminal connected to the reference voltage; and a third capacitor having a first terminal connected to the source of the fourth NMOS transistor, and a second terminal connected to the reference voltage. 9. The band-gap reference circuit of claim 7, wherein the first clock signal and the second clock signal are non-overlapping clock signals. 10. The band-gap reference circuit of claim 7, wherein the second IPTAT current generator comprises: a fourth PMOS transistor having a source connected to the supply voltage, a gate connected to the second PBIAS node, and a drain; a fifth PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the fourth PMOS transistor and a drain; a sixth PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the fifth PMOS transistor, and a drain connected to the first output node; a seventh capacitor having a first terminal connected to the supply voltage, and a second terminal connected to the gate of the sixth PMOS transistor; a second PNP transistor having an emitter connected to a drain of the fourth PMOS transistor, a base connected to the reference voltage, and a collector connected to the reference voltage; a second comparator circuit having an input coupled to the emitter of the second PNP transistor, second input coupled to the drain of the fifth PMOS transistor, and an output connected to the gates of the fourth and fifth PMOS transistors; an eighth capacitor having a first terminal connected to the emitter of the second PNP transistor, and a second terminal connected to the reference voltage; and a ninth capacitor having a first terminal connected to a drain of the fifth PMOS transistor, and a second terminal connected to the reference voltage; and a third switched capacitor resistor having a first node connected to the drain of the fifth PMOS transistor, and a second node connected to the reference voltage. 11. A current reference circuit that generates a reference current, the current reference circuit comprising: a band-gap reference circuit connected between a supply voltage and a reference voltage, the band-gap reference circuit generating a first bias voltage at a first PBIAS node, a second bias voltage at a second PBIAS node, and a third bias voltage at an NBIAS node, the band-gap reference circuit including at least one switched capacitor resistor, the band-gap reference circuit generating a band-gap reference voltage; a first PMOS transistor having a source connected to the supply voltage, a gate connected to the first PBIAS node, and a drain; a second PMOS transistor having a source connected to the supply voltage, a gate connected to the second PBIAS node, and a drain connected to the drain of the first PMOS transistor; a first NMOS transistor having a gate connected to the NBIAS node, a drain connected to the drain of the first PMOS transistor and a source connected to the reference voltage; a second NMOS transistor having a drain and a gate connected to the drain of the first PMOS transistor, and a source connected to the reference voltage; a third NMOS transistor having a gate connected to the drain of the first PMOS transistor, a source connected to the reference voltage, and a drain; a third PMOS transistor having a source connected to the supply voltage, and a drain and a gate connected to the drain of the third NMOS transistor; and a fourth PMOS transistor having a source connected to the supply voltage, a gate connected to the gate of the third PMOS transistor, and a drain from current is drawn.