초록 ▼

Systems and methods utilizing virtual input/output (VIO) modules in PLDS. One or more VIO modules are embedded in a PLD along with the user circuit to be controlled and monitored. The VIO module includes a control module that acts as a virtual input module for the user circuit, and can optionally in

Systems and methods utilizing virtual input/output (VIO) modules in PLDS. One or more VIO modules are embedded in a PLD along with the user circuit to be controlled and monitored. The VIO module includes a control module that acts as a virtual input module for the user circuit, and can optionally include a status module that acts as a virtual output module for the user circuit. A bi-directional data interface is provided between the user circuit and the VIO modules, and between the VIO modules and a communication module. The communication module is coupled through input/output pads of the PLD to an external communication link, and hence to a host computer in which resides software that controls the communication link. Thus, by interfacing with the host computer, a user can control the user circuit via the control modules and monitor output signals from the user circuit via the status modules.

대표청구항 ▼

What is claimed is: 1. A system, comprising: a communication link; a programmable logic device (PLD) configured to implement a user circuit, a virtual input/output (VIO) module bi-directionally coupled to the user circuit and comprising a control module for the user circuit, and a communication mod

What is claimed is: 1. A system, comprising: a communication link; a programmable logic device (PLD) configured to implement a user circuit, a virtual input/output (VIO) module bi-directionally coupled to the user circuit and comprising a control module for the user circuit, and a communication module bi-directionally coupled to the VIO module, the communication module being in electrical communication with the communication link; and a host computer in electrical communication with the communication link, the host computer including software for bi-directionally interfacing with the communication module via the communication link. 2. The system of claim 1, wherein the PLD is one of a group of PLDs consisting of: a field programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), a fuse-programmable device, and an anti-fuse programmable device. 3. The system of claim 1, wherein the communication link has a further electrical connection with the user circuit that bypasses the communication module and the VIO module. 4. The system of claim 1, wherein: the PLD is further configured to implement another logic circuit; and the communication link is further coupled to the another logic circuit. 5. The system of claim 1, wherein the communication link comprises at least one of the following: a direct-wired connection, a system bus, a remote access network, and a wireless network. 6. The system of claim 1, wherein the control module comprises a control shift chain coupled to receive signals from the communication module and to provide the signals to the user circuit. 7. The system of claim 1, wherein the control module comprises a pulse train generator configured to provide a predetermined train of pulses to the user circuit on receipt of a predetermined signal from the communication module. 8. The system of claim 1, wherein the control module is asynchronous. 9. The system of claim 1, wherein the control module is synchronous, the control module having an input clock terminal coupled to receive a clock signal from the user circuit. 10. The system of claim 1, wherein the VIO module further comprises a status module. 11. The system of claim 10, wherein the status module comprises a status shift chain coupled to receive signals from the user circuit and to provide the signals to the communication module. 12. The system of claim 10, wherein the status module comprises an asynchronous activity detector coupled to monitor an output signal from the user circuit. 13. The system of claim 10, wherein the status module comprises a synchronous activity detector coupled to monitor an output signal from the user circuit. 14. The system of claim 10, wherein the status module is synchronous, the status module having an input clock terminal coupled to receive a clock signal from the user circuit. 15. A programmable logic device (PLD), comprising: a plurality of input/output (I/O) pads; a user circuit implemented using a first group of programmable resources within the PLD; a virtual input/output (VIO) module comprising a control module for the user circuit and implemented using a second group of programmable resources within the PLD, the VIO module being bi-directionally coupled to the user circuit; and a communication module implemented using a third group of programmable resources within the PLD, the communication module being bi-directionally coupled to the VIO module and to the plurality of I/O pads. 16. The PLD of claim 15, wherein the PLD is one of a group of PLDS consisting of: a field programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), a fuse-programmable device, and an anti-fuse programmable device. 17. The PLD of claim 15, wherein the user circuit has a further electrical connection with the plurality of I/O pads that bypasses the communication module and the VIO module. 18. The PLD of claim 15, wherein the PLD further comprises an additional logic circuit implemented using a fourth group of programmable resources within the PLD, the additional logic circuit having an electrical connection with the plurality of I/O pads that bypasses the communication module and the VIO module. 19. The PLD of claim 15, wherein the communication module implements a JTAG interface. 20. The PLD of claim 15, wherein the control module comprises a control shift chain coupled to receive signals from the communication module and to provide the signals to the user circuit. 21. The PLD of claim 15, wherein the control module comprises a pulse train generator configured to provide a predetermined train of pulses to the user circuit on receipt of a predetermined signal from the communication module. 22. The PLD of claim 15, wherein the control module is asynchronous. 23. The PLD of claim 15, wherein the control module is synchronous, the control module having an input clock terminal coupled to receive a clock signal from the user circuit. 24. The PLD of claim 15, wherein the VIO module further comprises a status module. 25. The PLD of claim 24, wherein the status module comprises a status shift chain coupled to receive signals from the user circuit and to provide the signals to the communication module. 26. The PLD of claim 24, wherein the status module comprises an asynchronous activity detector coupled to monitor an output signal from the user circuit. 27. The PLD of claim 24, wherein the status module comprises a synchronous activity detector coupled to monitor an output signal from the user circuit. 28. The PLD of claim 24, wherein the status module is synchronous, the status module having an input clock terminal coupled to receive a clock signal from the user circuit. 29. A data communication medium storing a configuration data file for a programmable logic device (PLD), the PLD comprising a plurality of programmable resources and a plurality of input/output (I/O) pads, the configuration data file comprising: a first plurality of bits that configure a first subset of the plurality of programmable resources to implement a user circuit; a second plurality of bits that configure a second subset of the plurality of programmable resources to implement a virtual input/output (VIO) module comprising a control module for the user circuit and bi-directionally coupled to the user circuit; and a third plurality of bits that configure a third subset of the plurality of programmable resources to implement a communication module bi-directionally coupled to the VIO module and to the plurality of I/O pads. 30. The data communication medium of claim 29, wherein the PLD is one of a group of PLDs consisting of: a field programmable gate array (FPGA), a complex programmable logic device (CPLD), an application specific integrated circuit (ASIC), a fuse-programmable device, and an anti-fuse programmable device. 31. The data communication medium of claim 29, further comprising a fourth plurality of bits that configure a fourth subset of the plurality of programmable resources to implement an electrical connection between the user circuit and the plurality of I/O pads that bypasses the communication module and the VIO module. 32. The data communication medium of claim 29, wherein the communication module implements a JTAG interface. 33. A method of implementing a system using a programmable logic device (PLD), the system comprising a host computer and a communications link to the host computer, the method comprising: instantiating a user circuit in a design; instantiating a virtual input/output (VIO) module in the design, the VIO module comprising a control module for the user circuit and being bi-directionally coupled to the user circuit; implementing the design in the PLD using PLD implementation software; and adding the PLD to the system such that the user circuit is in bi-directional electrical communication with the host computer via the VIO module, the communication module, and the communication link. 34. The method of claim 33, further comprising: instantiating a communication module in the design. 35. The method of claim 33, further comprising: loading software to the host computer for interfacing with the communication module via the communication link. 36. The method of claim 35, further comprising: activating the communication link between the software and the communication module. 37. The method of claim 36, further comprising: providing control input data to the user circuit via the host computer. 38. The method of claim 36, wherein instantiating a VIO module comprises instantiating a status module, the method further comprising: retrieving status output data from the user circuit via the host computer. 39. The method of claim 33, wherein the steps of the method are performed in the order presented in the claim. 40. A method of implementing a user circuit in a programmable logic device (PLD), the method comprising: receiving a user circuit design description that includes a user circuit description and an instantiated virtual input/output (VIO) module, the VIO module comprising a control module for the user circuit and being bi-directionally coupled to the user circuit; implementing the user circuit design description in the PLD to provide an implemented design that includes the user circuit, the VIO module, and a communication module; and providing to the user a configuration file for the implemented design. 41. The method of claim 40, further comprising modifying the implemented design to alter connections between the user circuit and the control module without re-implementing the user design.