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Method and circuit for generating a higher order compensated bandgap voltage 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-003/16
  • G05F-003/08
출원번호 US-0836750 (2004-04-30)
발명자 / 주소
  • Erd챕lyi,J찼nos
  • Horv찼th,Andr찼s Vince
출원인 / 주소
  • Integration Associates Inc.
대리인 / 주소
    Francissen Patent Law, P.C.
인용정보 피인용 횟수 : 48  인용 특허 : 14

초록

A method and circuit are shown for generating a higher order compensated bandgap voltage is disclosed, in which a first order compensated bandgap voltage and a linearly temperature dependent voltage are generated. Thereafter, a difference between the linearly temperature dependent voltage and the fi

대표청구항

The invention claimed is: 1. A method for generating a higher order compensated bandgap voltage, the method comprising: generating a first order compensated bandgap voltage; generating a linearly temperature dependent voltage; generating a difference voltage based on the difference between the line

이 특허에 인용된 특허 (14)

  1. Doorenbos Jerry L. ; Jones David M., Bandgap reference curvature compensation circuit.
  2. Can Sumer, Bandgap reference voltage circuit with PTAT current source.
  3. Yang, Tsen-Shau, Bandgap reference voltage generator with V.sub.CC compensation.
  4. Price Burt L., Bandgap voltage reference based temperature compensation circuit.
  5. Marinca, Stefan, Bandgap voltage reference circuit with high power supply rejection ratio (PSRR) and curvature correction.
  6. Marshall Andrew (Dallas TX) Schmidt Thomas A. (Dallas TX) Teggatz Ross E. (Dallas TX), Compensation for low gain bipolar transistors in voltage and current reference circuits.
  7. Doyle James T., Low power digital CMOS compatible bandgap reference.
  8. Kimura Katsuji,JPX, MOS four-quadrant multiplier including the voltage-controlled-three-transistor V-I converters.
  9. Harrison, William Todd, Non-linear current generator for high-order temperature-compensated references.
  10. Fernald, Kenneth W., Processor based integrated circuit with a supply voltage monitor using bandgap device without feedback.
  11. Kimura Katsuji,JPX, Quarter-square multiplier based on the dynamic bias current technique.
  12. Kuttner Franz,ATX, Reference voltage source with compensated temperature dependency and method for operating the same.
  13. Thiel Frank L. (Richardson TX) Nguyen Baoson (Plano TX), Second order low temperature coefficient bandgap voltage supply.
  14. McGlinchey Gerard F. (Cupertino CA), Second order temperature compensated band cap voltage reference.

이 특허를 인용한 특허 (48)

  1. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.
  2. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.
  3. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.
  4. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.
  5. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.
  6. Nemecek, Craig, Conditional branching in an in-circuit emulation system.
  7. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
  8. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.
  9. Nemecek, Craig; Roe, Steve, External interface for event architecture.
  10. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.
  11. Anderson, Doug, Graphical user interface with user-selectable list-box.
  12. Seguine, Dennis R., Input/output multiplexer bus.
  13. Sequine, Dennis R., Input/output multiplexer bus.
  14. Horvath, Andras Vince, Low-power RF peak detector.
  15. Schwartsglass,Offer; Yurovich,Dov, Method and circuit for providing a temperature dependent current source.
  16. Moyal, Nathan; Stiff, Jonathon, Method and circuit for rapid alignment of signals.
  17. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
  18. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  19. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  20. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
  21. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
  22. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
  23. Kutz, Harold, Numerical band gap.
  24. Snyder, Warren S.; Mar, Monte, PSOC architecture.
  25. Snyder, Warren; Mar, Monte, PSOC architecture.
  26. Snyder, Warren S.; Mar, Monte, PSoC architecture.
  27. Snyder, Warren S.; Mar, Monte, PSoC architecture.
  28. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  29. Ogami, Kenneth Y., Power management architecture, method and configuration system.
  30. Snyder, Warren, Programmable microcontroller architecture.
  31. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
  32. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
  33. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
  34. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.
  35. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.
  36. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.
  37. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.
  38. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  39. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.
  40. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  41. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  42. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.
  43. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.
  44. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.
  45. Yoshio,Katsura, Thermal shut-down circuit.
  46. Beard, Paul; Woodings, Ryan Winfield, Touch wake for electronic devices.
  47. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.
  48. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.
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