Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited
Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited to a lithographic process dimension or adjusted accordingly. By dividing timing information gathering into sub-process, output from each of the sub-process may be combined with timing information provided with an embedded core to determine path delays.
대표청구항▼
The invention claimed is: 1. A timing modeling process for coupling different integrated circuit devices, comprising: obtaining gasket timing information from gasket wiring and logic for coupling the different integrated circuits, the obtaining of the gasket timing information including: obtaining
The invention claimed is: 1. A timing modeling process for coupling different integrated circuit devices, comprising: obtaining gasket timing information from gasket wiring and logic for coupling the different integrated circuits, the obtaining of the gasket timing information including: obtaining wire length information and associated signal name information; determining whether the wire length information is associated with signaling either to or from a core device; determining whether to wireload compensate the wire length information responsive to the signaling being from the core device; obtaining module timing information from modules for coupling the different integrated circuits; obtaining core device timing information for one of the different integrated circuits; and assembling the gasket timing information, the module timing information and the core device timing information for respective signal paths. 2. The timing modeling process according to claim 1, wherein the step of obtaining the module timing information comprises: modeling at least one module on a component level to obtain resistance and capacitance values for the at least one module; generating a network list for the at least one module in response to the resistance and capacitance values obtained; and simulating operation of the at least one module in response to the network list to generate the module timing information for the at least one module. 3. The timing modeling process according to claim 1, wherein the step of obtaining the gasket timing information comprises: obtaining interconnect information; modeling the interconnect information to provide associated resistance and capacitance values; and generating a network list in response to the resistance and capacitance values. 4. The timing modeling process according to claim 3, wherein the step of obtaining the gasket timing information comprises: placing schematic elements associated with the interconnect information; routing interconnects for coupling the schematic elements; and generating an interconnect report in response to the interconnects routed. 5. The timing modeling process according to claim 4, wherein the obtaining of the wire length information includes obtaining the wire length information from the interconnect report; and wherein the step of obtaining the gasket timing information comprises: populating the network list with the wire length information of the interconnect report; and simulating the network list populated with the wire length information. 6. A timing modeling process for an embedded device gasket module for coupling an embedded device and a host device, comprising: providing a first database for the embedded device gasket module, the first database including information on discrete elements for coupling the embedded device to the host device; placing the discrete elements; routing interconnects for interconnecting the discrete elements; generating an interconnect report in response to the interconnects routed; obtaining interconnect relationship information for interconnecting the discrete elements; obtaining first resistance and capacitance values for the discrete elements; generating a first network list in response to the interconnect relationship information obtained; populating the first network list with wire length information from the interconnect report to provide a second network list; modeling the wire length information and the interconnects to obtain second resistance and capacitance values; simulating the discrete elements as interconnected in response to the second network list to generate gasket logic and interconnect timing information; providing a second database, the second database comprising sub-module information for coupling the embedded device to the host device; modeling the sub-modules information to obtain third resistance and capacitance values; generating a third network list for the third resistance and capacitance values obtained; simulating the sub-modules in response to the third network list to generate sub-module timing information for the sub-modules; obtaining embedded device timing information for the embedded device; and assembling the gasket logic interconnect timing information, the sub-module timing information and the embedded device timing information for respective signal paths. 7. The timing modeling process according to claim 6, wherein the step of assembling comprises adding delays for each of the respective signal paths to obtain a total delay for each of the respective signal paths. 8. The timing modeling process according to claim 6, wherein the first database is provided from a circuit simulation language description of the embedded device gasket module. 9. The timing modeling process according to claim 6, wherein the second database is provided from a physical layout database of the host device. 10. The timing modeling process according to claim 9, wherein the second database is for a first lithographic dimension, the first lithographic dimension is different from a second lithographic dimension for the embedded device. 11. The timing modeling process according to claim 10, wherein the step of modeling the sub-modules to obtain third resistance and capacitance values comprises applying a shrink factor to provide the third resistance and capacitance values obtained, the shrink factor dependent on the difference between the first lithographic dimension and the second lithographic dimension. 12. The timing modeling process according to claim 11, wherein the core device timing information is obtained from standard data format files. 13. The timing modeling process according to claim 12, wherein the core device timing information comprises setup time information for the embedded device. 14. The timing modeling process according to claim 13, wherein the core device timing information comprises hold time information for the embedded device. 15. The timing modeling process according to claim 12, wherein the core device timing information comprises clock-to-out time information for the embedded device. 16. The timing modeling process according to claim 6, wherein the step of simulating the sub-modules in response to the third network list is done with a static timing analysis computer program. 17. The timing modeling process according to claim 6, wherein the step of simulating the discrete elements and interconnects in response to the second network list is done with a device level circuit simulator computer program. 18. The timing modeling process according to claim 6, wherein the steps of placing the discrete elements, routing interconnects and generating the interconnect report are done with a place and route computer program. 19. The timing modeling process according to claim 18, wherein the interconnect report includes length of each of the interconnects. 20. A computer-readable medium having stored thereon computer-executable instructions for performing a method, the method comprising steps of: obtaining gasket timing information from gasket wiring and logic for coupling different integrated circuits, the obtaining of the gasket timing information including: obtaining wire length information and associated signal name information; determining whether the wire length information is associated with signaling either to or from a core device; and determining whether to wireload compensate the wire length information responsive to the signaling being from the core device; obtaining module timing information from modules for coupling the different integrated circuits; obtaining core device timing information for one of the different integrated circuits; and assembling the gasket timing information, the module timing information and the core device timing information for respective signal paths. 21. A computer-readable medium having stored thereon computer-executable instructions for performing a method, the method comprising steps of: accessing a first database for an embedded device gasket module, the first database including information on discrete elements for coupling an embedded device to a host device; placing the discrete elements; routing interconnects for interconnecting the discrete elements; generating an interconnect report in response to the interconnects routed; obtaining interconnect relationship information for interconnecting the discrete elements; obtaining first resistance and capacitance values for the discrete elements; generating a first network list in response to the interconnect relationship information obtained; populating the first network list with wire length information from the interconnect report to provide a second network list; modeling the wire length information and the interconnects to obtain second resistance and capacitance values; simulating the discrete elements as interconnected in response to the second network list to generate gasket logic and interconnect timing information; accessing a second database, the second database comprising sub-module information for coupling the embedded device to the host device; modeling the sub-modules information to obtain third resistance and capacitance values; generating a third network list for the third resistance and capacitance values obtained; simulating the sub-modules in response to the third network list to generate sub-module timing information for the sub-modules; obtaining embedded device timing information for the embedded device; and assembling the gasket logic interconnect timing information, the sub-module timing information and the embedded device timing information for respective signal paths. 22. A system for timing modeling and analysis for coupling different integrated circuit devices, comprising: a computer, the computer comprising a timing modeling module and a timing analysis module; the timing modeling module for: obtaining gasket timing information from gasket wiring and logic for coupling the different integrated circuits; obtaining module timing information from modules for coupling the different integrated circuits; obtaining core device timing information for one of the different integrated circuits; assembling the gasket timing information, the module timing information and the core device timing information for respective signal paths; the timing analysis module for analyzing the gasket timing information, the module timing information and the core device timing information assembled, wherein the gasket timing information comprises wire length and associated signal name, wherein the timing analysis module is further for: obtaining the wire length and the associated signal name from the gasket timing information; and determining whether the wire length is for a signal originating from one of the different integrated circuits in response to the associated signal name to determine whether to wireload compensate the wire length. 23. The system according to claim 22, wherein the different integrated circuits are an embedded core in a host integrated circuit. 24. The system according to claim 23, wherein if the wire length is not for carrying the signal originating from the embedded core, selecting a wire line model for at least one conductive line associated with the wire length; selecting a driver in at least partial response to the wire length; and selecting the simulation template in response to the driver selected. 25. The system according to claim 23, wherein if the wire length is for carrying the signal originating from the embedded core, determining an adjusted wire length from the wire length; determining if the adjusted wire length is less than a predetermined length; and selecting the simulation template in response to whether the adjusted wire length is less than the predetermined length. 26. The system according to claim 23, wherein the timing analysis module is further for: obtaining a wire list including the wire length; selecting a condition from which the wire list was prepared; accessing embedded core timing information in response to the condition selected; classifying signals including the signal as one of input signals to the embedded core and output signals from the embedded core in response to the wire list; and determining whether the signals classified are for an input group or an output group. 27. The system according to claim 26, wherein for the input group, the timing analysis module is configured to search input signal path timing information from the embedded core timing information to obtain rise time information and fall time information. 28. The system according to claim 26, wherein for the output group, the timing analysis module is configured to search output signal path timing information from the embedded core timing information to obtain rise time information and fall time information. 29. The system according to claim 26, wherein for the wire lengths not for carrying the signals originating from the embedded core, the timing analysis module is configured to: select wire line models for conductive lines associated with the wire lengths; select drivers in at least partial response to the associated signal names; and select from a first group of simulation templates in response to the drivers selected. 30. The system according to claim 26, wherein for the wire lengths for carrying the signals originating from the embedded core, the timing analysis module is configured to: determine adjusted wire lengths from the wire lengths; determine if the adjusted wire lengths are less than a predetermined length; select from a second group of simulation templates in response to a first portion of the adjusted wire lengths being less than the predetermined length; and select from a third group of simulation templates in response to a second portion of the adjusted wire lengths not being less than the predetermined length. 31. The system according to claim 23, wherein the timing analysis module is further for: obtaining wire lengths including the wire length and associated signal names including the signal name from the gasket timing information; and determining whether the wire lengths are for signals including the signal originating from the embedded core in response to the associated signal names.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (80)
Sambamurthy Namakkal S. (San Jose CA) Lai Woo-Ping (San Jose CA) VanGilder John P. (Sunnyvale CA), Apparatus and method for full-duplex ethernet communications.
Sambamurthy Namakkal S. (San Jose CA) Lai Woo-Ping (San Jose CA) VanGilder John P. (Sunnyvale CA), Apparatus and method for full-duplex ethernet communications.
Muraoka Hiroshi (Kawasaki JPX) Fujisaku Kiminori (Sagamihara JPX), Apparatus for suspending the bus cycle of a microprocessor by inserting wait states.
Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Hartmann Alfred C., Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals.
Clifford Hessel ; Paul E. Voglewede ; Michael E. Kreeger ; Christopher D. Mackey ; Scott E. Marks ; Alfred W. Pietzold, III ; Louis M. Orsini ; John E. Gorton, Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor.
Lien Jung-Cheun ; Huang Eddy Chieh ; Sun Chung-yuan ; Feng Sheng, Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template.
Colwell Robert P. (Portland OR) Papworth David B. (Beaverton OR) Fetterman Michael A. (Hillsboro OR) Glew Andrew F. (Hillsboro OR) Hinton Glenn J. (Portland OR) Coward Stephen M. (Aloha OR) Chen Grac, Hybrid execution unit for complex microprocessor.
Andrews William B. ; Britton Barry K. ; Hickey Thomas J. ; Modo Ronald T. ; Nguyen Ho T. ; Schadt Lorraine L. ; Singh Satwant, Hybrid programmable gate arrays.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Lien Jung-Cheun ; Feng Sheng ; Sun Chung-yuan ; Huang Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.
Sutherland James (Santa Clara CA) Garverick Timothy L. (Cupertino CA) Takiar Hem P. (Fremont CA) Reyling ; Jr. George F. (Saratoga CA), Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module.
Rostoker Michael D. (Boulder Creek CA) Gluss David (Woodside CA) Harrington Tom (Mountain View CA), Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC.
Jose Maria Insenser Farre ES; Julio Faura Enriquez ES, Microprocessor based mixed signal field programmable integrated device and prototyping methodology.
Barry K. Britton ; Ravikumar Charath ; Zheng Chen ; James F. Hoff ; Cort D. Lansenderfer ; Don McCarley ; Richard G. Stuby, Jr. ; Ju-Yuan D. Yang, Multi-master multi-slave system bus in a field programmable gate array (FPGA).
Ang, Roger; Ahuja, Atul; Lulla, Mukesh T.; Borkovic, Drazen; Small, Brian D.; Tralka, Charles C.; Chan, Andrew K.; Yee, Kevin K., Programmable device with an embedded portion for receiving a standard circuit design.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Fransisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.
Patel, Rakesh H.; Turner, John E., Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M. ; Tran Giap H., Tileable and compact layout for super variable grain blocks within FPGA device.
Pressly Matthew D. ; Giles Grady L. ; Crouch Alfred L., Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation.
Boshart,Shawn; Krska,Jee Hoon; Lentz,John Gavin; Williams,Joshua, Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies.
Herron,Nigel G.; Ansari,Ahmad R.; Douglass,Stephen M.; Correale, Jr.,Anthony; DeBruyne,Leslie M., Speed verification of an embedded processor in a programmable logic device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.