$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Microelectronic component and assembly having leads with offset portions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
  • H01L-021/48
  • H01L-021/50
출원번호 US-0301188 (2002-11-21)
발명자 / 주소
  • Khandros,Igor Y.
  • DiStefano,Thomas H.
출원인 / 주소
  • Tessera, Inc.
대리인 / 주소
    Lerner, David, Littenberg, Krumholz &
인용정보 피인용 횟수 : 16  인용 특허 : 199

초록

A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semico

대표청구항

The invention claimed is: 1. A method of making a microelectronic assembly, comprising: a) juxtaposing a microelectronic component, comprising: 1) a dielectric layer defining at least one opening; and 2) a plurality of leads attached to the dielectric layer so as to extend across the at least one o

이 특허에 인용된 특허 (199)

  1. Mahulikar Deepak (Meriden CT) Popplewell James M. (Guilford CT), Aluminum alloy semiconductor packages.
  2. Nickel Donald F. (West Columbia SC), Apparatus and method for stacking integrated circuit devices.
  3. Yamamoto Hiroshi (Ibaragi JPX), Arrangement of a semiconductor device for use in a card.
  4. Mulholland Wayne A. (Plano TX) Quinn Daniel J. (Carrollton TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX), Automatic assembly of integrated circuits.
  5. Matunami Mituo (Izumisano JA), Beam lead formation method.
  6. Buckley ; III Frederick (San Jose CA) Blomgren James S. (San Jose CA), Bi-planar multi-chip module.
  7. Bajorek Christopher H. (Goldens Bridge NY) Chance Dudley A. (Danbury CT) Ho Chung W. (Chappaqua NY), Capacitive chip carrier and multilayer ceramic capacitors.
  8. Hoppe, Joachim; Haghiri-Tehrani, Yahya, Carrier element for IC-modules.
  9. Haghiri-Tehrani Yahya (Munich DEX) Hoppe Joachim (Munich DEX), Carrier element for an IC module.
  10. Bourdelaise Robert A. (Crofton MD) Harris David B. (Columbia MD) Harris Denise B. (Columbia MD) Olenick John A. (Columbia MD), Cavity-down chip carrier with pad grid array.
  11. Jones Kenneth L. (Escondido CA), Ceramic package and method for making same.
  12. Yew Chee Kiang,SGX ; Swee Yong Khim,SGX ; Chan Min Yu,SGX ; Ong Pang Hup,SGX ; Coyle Anthony, Chip size integrated circuit package.
  13. Carey David H. (Austin TX) Whalen Barry H. (Austin TX), Compact adapter package providing peripheral to area translation for an integrated circuit chip.
  14. Baker Thomas E. (Northboro MA) Krasnow S. Bert (Lake Worth FL) Silverman Richard A. (Berlin MA), Compliant layer printed circuit board.
  15. Gilleo Kenneth B. ; Grube Gary W. ; Mathieu Gaetan, Compliant semiconductor chip assemblies and methods of making same.
  16. Dehaine ; Gerard, Conditioning supports of micro-plates of integrated circuits.
  17. Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Sakaguchi Suguru (Chigasaki JPX), Connecting structure for electronic part and method of manufacturing the same.
  18. Noro Takanobu (Yokohama JPX) Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Kanda Naoya (Yokohama JPX) Sakaguchi Suguru (Yokohama JPX) Murata Akira (Tokyo JPX), Connecting structure of electronic part and electronic device using the structure.
  19. Patraw Nils E. (Redondo Beach CA), Connector system for coupling to an integrated circuit chip.
  20. Haghiri-Tehrani Yahya (Munich DEX), Data carrier having an integrated circuit and a method for producing the same.
  21. Matta Farid (Mountain View CA) Douglas Kevin C. (San Mateo CA), Demountable tape-automated bonding system.
  22. Carson John C. (Corona Del Mar CA) Clark Stewart A. (Irvine CA), Detector array module fabrication process.
  23. Prevost Michel (Le Plessis-Robinson FRX), Device for interconnection between and integrated circuit and an electrical circuit.
  24. Grube Gary W. (Washingtonville NY) Khandros Igor Y. (Peekskill NY), Direct attachment of semiconductor chips to a substrate with a substrate with a thermoplastic interposer.
  25. Lee James C. K. (Los Altos Hills CA) Ahmad Arshad (San Jose CA) Castro Myrna E. (Milpitas CA) Tung Francisca (Los Gatos CA), Double-sided hybrid high density circuit board and method of making same.
  26. Beaman Brian S. (Hyde Park NY), Elastomeric area array interposer.
  27. Huckabee Bill F. (Santa Cruz CA) Wright William L. (Saratoga CA), Electric circuit packaging member.
  28. Zifcak Mark S. (Putnam CT) Kosa Bruce G. (Woodstock CT), Electrical circuit board interconnect.
  29. Smith Robert T. (Roundrock TX) Chung Chang-Hwa (Austin TX), Electrical interconnect tape.
  30. Roth Norman J. (Kokomo IN), Electrical interconnection having angular lead design.
  31. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  32. Eden Richard C. (Thousand Oaks CA), Electronic circuit and method with thermal management.
  33. Bernardoni Lonnie L. (Coral Springs FL) Zollo James A. (Coral Springs FL) Thompson Kenneth R. (Sunrise FL), Electronic component assembly.
  34. Bregman Mark F. (Ridgefield CT) Horton Raymond R. (Dover Plains NY) Lanzetta Alphonso P. (Marlboro NY) Noyan Ismail C. (Peekskill NY) Palmer Michael J. (Walden NY) Tong Ho-Ming (Yorktown Heights NY), Electronic substrate multiple location conductor attachment technology.
  35. Noyori Masaharu (Neyagawa JPX) Fujimoto Hiroaki (Neyagawa JPX), Electronics circuit device and method of making the same.
  36. Jacobs Scott L. (Apex NC), Extended integration semiconductor structure with wiring layers.
  37. Freyman Bruce J. (Sunrise FL) Miles Barry M. (Plantation FL) Flaugher Jill L. (Margate FL), Fabrication of pad array carriers from a universal interconnect structure.
  38. Igor Y. Khandros ; Thomas H. Distefano, Face-up semiconductor chip assemblies.
  39. Khandros Igor Y. ; Distefano Thomas H., Face-up semiconductor chip assembly.
  40. Takekawa Kouichi (Tokyo JPX) Urushima Michitaka (Tokyo JPX), Film carrier semiconductor device.
  41. Ugon Michel (Plaisir FRX), Flat package for integrated circuit devices.
  42. McBride Donald G. (Binghamton NY) Ellis Theron L. (Vestal NY), Flexible carrier for an electronic device.
  43. McBride Donald G. (Binghamton NY) Ellis Theron L. (Vestal NY), Flexible carrier for an electronic device.
  44. Canestaro Michael J. (Endicott NY) Summa William J. (Endwell NY), Flexible electrical connection and method of making same.
  45. Canestaro Michael J. (Endicott NY) Summa William J. (Endwell NY), Flexible electrical connection and method of making same.
  46. Clementi Robert J. (Binghamton NY) Gazdik Charles E. (Endicott NY) Lafer William (Chenango Bridge NY) Lovesky Roy L. (Vestal NY) McBride Donald G. (Binghamton NY) Munson Joel V. (Port Crane NY) Skarv, Flexible film semiconductor chip carrier.
  47. Sasaki Takahide (Kanagawa) Terashima Jun (Kanagawa) Yamanouchi Haruhiko (Kanagawa JPX), Flexible printed circuit board.
  48. Carey David H. (Austin TX), Flip substrate for chip mount.
  49. Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL) Papageorge Marc V. (Plantation FL), Flip-chip package for integrated circuits.
  50. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY) Seraphim Donald P. (Vestal NY) Toole Patrick A. (Westport CT), Full panel electronic packaging structure.
  51. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY) Seraphim Donald P. (Vestal NY) Toole Patrick A. (Westport CT), Full panel electronic packaging structure and method of making same.
  52. Jacobs Scott L. (Chester VA) Nihal Perwaiz (Hopewell Junction NY) Ozmat Burhan (Peekskill NY) Schnurmann Henri D. (Monsey NY), High performance integrated circuit packaging structure.
  53. Prokop Jon S. (Richardson TX), High terminal count integrated circuit device package.
  54. Fox ; III Angus C. (Boise ID) Farnworth Warren M. (Nampa ID), High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vi.
  55. Carson John C. (Corona del Mar CA) Clark Stewart A. (Irvine CA), High-density electronic processing package-structure and fabrication.
  56. Ackermann Karl-Peter (Niederrohrdorf CHX) Berner Gianni (Baden CHX), Highly integrated circuit and method for the production thereof.
  57. Inoue Yukihiro (Kashihara JPX), Installation of a semiconductor chip on a glass substrate.
  58. Kodama Hironori (Hitachi JPX) Ogihara Satoru (Hitachi JPX) Arakawa Hideo (Hitachi JPX) Inoue Hirokazu (Ibaraki JPX) Yasutomi Yoshiyuki (Katsuta JPX) Miyoshi Tadahiko (Hitachi JPX), Installation structure of integrated circuit devices.
  59. Hubbard John B. (Watton-on-Thames GB2), Integrated circuit chip carrier.
  60. Sinnadurai F. Nihal (Woodbridge GB2) Cook Anthony J. (Dippenhall ; Near Farnham GB2) Gurnett Keith W. (Bracknell GB2), Integrated circuit chip carrier.
  61. Sinnadurai F. Nihal (Woodbridge GB2) Cook Anthony J. (Dippenhall ; Nr Farnham GB2) Gurnett Keith W. (Bracknell GB2), Integrated circuit chip carrier.
  62. Thompson Kenneth R. (Sunrise FL) Banerji Kingshuk (Plantation FL) Mullen ; III William B. (Boca Raton FL), Integrated circuit chip carrier.
  63. Whitehead Graham K. (Ipswich GB2) Taylor Kenneth (East Barnet GB2), Integrated circuit chip carrier.
  64. Marcantonio Gabriel (Nepean CAX), Integrated circuit chip package.
  65. Eide Floyd (Huntington Beach CA), Integrated circuit chip stacking.
  66. Tai King L. (Berkeley Heights NJ), Integrated circuit chip-and-substrate assembly.
  67. Ciccio Joseph A. (Winchester MA) Thun Rudolf E. (Carlisle MA) Fardy Harry J. (Chelmsford MA), Integrated circuit device package interconnect means.
  68. Cardashian Vahram S. (Plymouth MN) Loy Jerald M. (Anoka MN) Mills Frank S. (Minneapolis MN), Integrated circuit interconnector.
  69. Hayward James (Mountain View CA) Brown Candice H. (San Jose CA), Integrated circuit lead frame assembly containing voltage bussing and distribution to an integrated circuit die using ta.
  70. Frankeny Jerome A. (Taylor TX) Frankeny Richard F. (Austin TX) Hermann Karl (Austin TX) Imken Ronald L. (Round Rock TX), Integrated circuit packaging using flexible substrate.
  71. Wilson Arthur M. (Richardson TX), Integrated circuit product having a polyimide film interconnection structure.
  72. Hinrichsmeyer Kurt (Sindelfingen DEX) Straehle Werner (Dettenhausen VT DEX) Kelley ; Jr. Gordon A. (Essex Junction VT) Noth Richard W. (Fairfax VT), Integrated semiconductor chip package.
  73. Robillard David R. (Westboro MA) Michaels Robert L. (Marlboro MA), Integrated test and assembly device.
  74. Walter Jackie A. (Sunnyvale CA), Interconnect tape for use in tape automated bonding.
  75. Eytcheson Charles T. (Kokomo IN), Interconnection lead having individual spiral lead design.
  76. Patraw Nils E. (Redondo Beach CA), Inverted chip carrier.
  77. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  78. Phy William S. (Los Altos Hills CA), Lead format for tape automated bonding.
  79. Mallik Debendra (Chandler AZ) Bhattacharyya Bidyut K. (Chandler AZ), Lead grid array integrated circuit.
  80. Wojnar Jeffrey S. (Mercer County NJ) McCusker Joseph H. (Mercer County NJ), Leadless ceramic chip carrier printed wiring board adapter.
  81. Mullen ; III William B. (Boca Raton FL) Urbish Glenn F. (Coral Springs FL) Freyman Bruce J. (Plantation FL), Leadless pad array chip carrier.
  82. Krajewski Nicholas J. (Chippewa Falls WI) Johnson David J. (Chippewa Falls WI) Kunstmann Arthur O. (Weyerhauser WI), Memory metal electrical connector.
  83. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Welles ; II Kenneth B. (Schenectady NY), Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer.
  84. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Welles ; II Kenneth B. (Schenectady NY), Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer.
  85. Spanjer Keith G. (Scottsdale AZ), Method for applying material to a semiconductor wafer.
  86. Bregman Mark F. (Ridgefield CT) Horton Raymond R. (Dover Plains NY) Lanzetta Alphonso P. (Marlboro NY) Noyan Ismail C. (Peekskill NY) Palmer Michael J. (Walden NY) Tong Ho-Ming (Yorktown Heights NY), Method for bonding dielectric mounted conductors to semiconductor chip contact pads.
  87. Lakritz, Mark N.; Ordonez, Jose; Tubiola, Peter J., Method for forming elongated solder connections between a semiconductor device and a supporting substrate.
  88. Hoppe Joachim (Munich DEX), Method for producing an identification card with an integrated circuit.
  89. Wilson Arthur M. (Richardson TX), Method for producing an integrated circuit product having a polyimide film interconnection structure.
  90. Kunieda Shin-ichi (Sacramento CA) Ozawa Masahide (Citrus Heights CA), Method for testing semiconductor devices.
  91. Ohno Hideshi (Sayama JPX), Method of assembling semiconductor integrated circuit.
  92. Burns Carmen D. (10210 Holme-Lacey La. Austin ; Travis County TX 78750) Roane Jerry M. (101 Laurelwood Dr. South Austin ; Travis County TX 78733) Cady James W. (6803 Bayridge Ter. Austin ; Travis Cou, Method of assembling ultra high density integrated circuit packages.
  93. Reche John J. (Ventura CA), Method of fabricating hybrid circuit structures.
  94. Razon Eli ; Von Seggern Walter, Method of forming a chip scale package, and a tool used in forming the chip scale package.
  95. Jacobs Scott L. (Apex NC), Method of making a extended integration semiconductor structure.
  96. Rai Akiteru (Osaka JPX) Yamamura Keiji (Nara JPX) Nukii Takashi (Nara JPX), Method of making a hybrid semiconductor device.
  97. Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Redondo Beach CA) Nicholas Henry T. (Redondo Beach CA), Method of making an adaptive configurable gate array.
  98. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Method of making an ultra high density pad array chip carrier.
  99. Kimura Mitsuru (Tokyo JPX) Nakakita Shoji (Tokyo JPX), Method of manufacturing a multichip package with increased adhesive strength.
  100. Daigle Robert (Sterling CT) Malbaurn Samuel (Dayville CT) Noddin David (Eau Claire WI), Method of manufacturing a multilayer circuit board.
  101. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of packaging and powering integrated circuit chips and the chip assembly formed thereby.
  102. Smith Kenneth R. (Aloha OR) Johnston Kent H. (Beaverton OR) LaRue George S. (Beaverton OR) Mueller Robert A. (Portland OR) Tabor Steven A. (Aptos CA), Method of packaging integrated circuit chips, and integrated circuit package.
  103. Ootsuki Hideaki (Amagasaki JPX) Takada Mitsuyuki (Amagasaki JPX) Kokogawa Toru (Amagasaki JPX) Takasago Hayato (Amagasaki JPX), Method of packaging semiconductor device.
  104. Khandros Igor Y. ; DiStefano Thomas H., Methods of making semiconductor chip assemblies.
  105. Khandros Igor Y. ; Distefano Thomas H., Methods of making semiconductor chip assemblies.
  106. Funari Joseph (Vestal NY), Micro-surface welding.
  107. Smith John W., Microelectronic connections with liquid conductive elements.
  108. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA), Microelectronic mounting with multiple lead deformation and bonding.
  109. Harada Yuji (Tokyo JPX) Shinohara Hayato (Yokohama JPX), Mounting assembly and mounting method for an electronic component.
  110. Mehta Mahendra C. (Palm Beach Gardens FL), Mounting of semiconductor chips on a plastic substrate.
  111. DiStefano Thomas H. (Bronxville NY) Khandros Igor Y. (Peekskill NY) Grube Gary W. (Monroe NY), Multi-layer circuit construction methods with customization features.
  112. Lynch Brian ; McCormick John, Multi-layer tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparat.
  113. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging configuration and method.
  114. Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY), Multichip integrated circuit packaging method.
  115. Elder Richard A. (Dallas TX) Johnson Randy (Carrollton TX) Frew Dean L. (Garland TX) Wilson Arthur M. (Dallas TX), Non-destructive burn-in test socket for integrated circuit die.
  116. Rostoker Michael D. ; Pasch Nicholas F., Optically transmissive preformed planar structures.
  117. Hallenbeck Gary A. (Fairport NY) Janson ; Jr. Wilbert F. (Shortsville NY) Jones William B. (Rochester NY), Optoelectronic device component package.
  118. Hill William H. (Carlsbad CA) Cawelti Dale W. (Carlsbad CA), Orthogonal bonding method and equipment.
  119. Worp Nicolaas H. (Margate FL) Freyman Bruce J. (Plantation FL) Conrath Kurt C. (Lauderhill FL), Overmolded semiconductor package with anchoring means.
  120. McShane Michael B. (Austin TX) Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Packaged semiconductor device having a low cost ceramic PGA package.
  121. Carlson Randolph S. (Carson City NV), Packaging system for stacking integrated circuits.
  122. Carlson Randolph S. (Carson City NV) Chase Charles P. (Carson City NV), Packaging system for stacking integrated circuits.
  123. Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Pad array carrier IC device using flexible tape.
  124. Grabbe Dimitry G. (2160 Rosedale Ave. Middletown PA 17057), Perimeter independent precision locating member.
  125. Carey David H. (Austin TX) Whalen Barry H. (Austin TX), Peripheral to area adapter with protective bumper for an integrated circuit chip.
  126. Phelps ; Jr. Douglas W. (Burlington VT) Redmond Robert J. (Essex Junction VT) Ward William C. (Burlington VT), Peripheral/area wire bonding technique.
  127. Mu Albert T. (San Jose CA), Pin grid array package structure.
  128. Hirata Atsuomi (Nara JPX) Mamiya Hirokuni (Yokkaichi JPX), Plastic molded chip carrier package and method of fabricating the same.
  129. Grabbe Dimitry G. (Lisbon Falls ME), Power, ground and decoupling structure for chip carriers.
  130. Casey John F. (Colorado Springs CO) Vyne Robert L. (Tempe AZ), Preferred device orientation on integrated circuits for better matching under mechanical stress.
  131. Enochs Raymond S. (Hillsboro OR), Pressure interconnect package for integrated circuits.
  132. Meyer James A. (Campbell CA) Mikalauskas Frank (San Jose CA) Parks Howard L. (Los Gatos CA), Pressurized interconnection system for semiconductor chips.
  133. Reding Bennett J. (Colorado Springs CO) McIver Chandler H. (Tempe AZ), Pretestable double-sided tab design.
  134. Jacobi John W. (Fort Collins CO), Process for bonding integrated circuit components.
  135. Yeh Kwang (Huntington Beach CA) Valle Manuel B. (Covina CA), Process for fabricating compliant layer board with selectively isolated solder pads.
  136. Rostoker Michael D. (San Jose CA) Pasch Nicholas F. (Pacifica CA), Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interpos.
  137. Phy William S. (Los Altos Hills CA), Process of forming a compliant lead frame for array-type semiconductor packages.
  138. Quinn ; Daniel J. (Carrollton TX) Mulholland Wayne A. (Plano TX) Bond Robert H. (Carrollton TX) Olla Michael A. (Flower Mound TX) Cupples Jerry S. (Carrollton TX) Tsitovsky Ilya L. (Farmers Branch TX, Process of forming integrated circuits with contact pads in a standard array.
  139. Bhattacharyya Arup (Essex Junction VT) Wen Ho Chung (Chappaqua NY), Process of making interconnection structure for semiconductor device.
  140. Bednarz George A. (Plano TX) Smith Reginald W. (Arlington TX) Roeding Gretchen W. (Carrollton TX) Test Howard R. (Plano TX), Process of packaging a semiconductor device with reduced stress forces.
  141. Tsubosaki Kunihiro (Hino JPX) Murakami Gen (Machida JPX) Sakuta Toshiyuki (Hamura JPX) Ishihara Masamichi (Hinode JPX) Ito Satoru (Tokyo JPX) Mori Yasuo (Ohme JPX), Resin-encapsulated semiconductor device.
  142. Oguchi Satoshi (Ohme JPX) Ishihara Masamichi (Hamura-machi JPX) Ito Kazuya (Hamura-machi JPX) Murakami Gen (Tama JPX) Anjoh Ichiro (Koganei JPX) Sakuta Toshiyuki (Ohme JPX) Yamaguchi Yasunori (Ohme J, Sealed stacked arrangement of semiconductor devices.
  143. Grube Gary (Monroe NY) Khandros Igor (Peekskill NY) Mathieu Gaetan (Carmel NY), Semiconductor chip assemblies and components with pressure contact.
  144. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies and methods of making same.
  145. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies having interposer and flexible lead.
  146. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with face-up mounting and rear-surface connection to substrate.
  147. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies with fan-in leads.
  148. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Semiconductor chip assemblies, methods of making same and components for same.
  149. Grabbe Dimitry G. (Middletown PA), Semiconductor chip carrier system.
  150. Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Beck Richard L. (Cupertino CA) Quinn Robert F. (Cupertino CA) Sochor Jerzy R. (San Jose CA), Semiconductor chip interface.
  151. Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Amdahl Carlton G. (Saratoga CA) Beck Richard L. (Cupertino CA), Semiconductor chip module interconnection system.
  152. Burt Roy J. (Sunnyvale CA), Semiconductor chip mounting system.
  153. Khandros Igor Y. ; Distefano Thomas H., Semiconductor chip package with center contacts.
  154. Sakuta Toshiyuki (Hamura JPX) Miyazawa Kazuyuki (Iruma JPX) Oguchi Satoshi (Ohme JPX) Kaneda Aizo (Yokohama JPX) Mitani Masao (Yokohama JPX) Nakamura Shozo (Yokohama JPX) Nishi Kunihiko (Kokubunji JP, Semiconductor device.
  155. Yamaji Yasuhiro (Kawasaki JPX), Semiconductor device.
  156. Murakami Gen (Machida JPX) Gappa Takeshi (Ohme JPX), Semiconductor device and a method of producing the same.
  157. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX), Semiconductor device and its manufacture.
  158. Chuichi Miyazaki JP; Yukiharu Akiyama JP; Masanori Shibamoto JP; Tomoaki Kudaishi JP; Ichiro Anjoh JP; Kunihiko Nishi JP; Asao Nishimura JP; Hideki Tanaka JP; Ryosuke Kimoto JP; Kunihiro Tsu, Semiconductor device and manufacturing method thereof.
  159. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Semiconductor device and method of producing semiconductor device.
  160. Sahara Kunizo (Tokyo JPX) Otsuka Kanji (Higashiyamato JPX) Ishida Hisashi (Higashiyamato JPX), Semiconductor device and process for producing the same.
  161. McCormick John (Redwood City CA), Semiconductor device assembly including power or ground plane which is provided on opposite surface of insulating layer.
  162. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX) Wilson Howard P. (Austin TX), Semiconductor device having a pad array carrier package.
  163. Long Jon M. (Livermore CA) Sidorovsky Rachel S. (San Jose CA) Steidl Michael J. (San Jose CA) Murphy Adrian (San Jose CA) Sen Bidyut (Milpitas CA), Semiconductor device package and method of making such a package.
  164. Tsubosaki Kunihiro (Hino JPX) Tanimoto Michio (Kokubunji JPX) Nishi Kunihiko (Kokubunji JPX) Ichitani Masahiro (Kodaira JPX) Koike Shunji (Kodaira JPX) Suzuki Kazunari (Tokyo JPX) Kimoto Ryosuke (Tac, Semiconductor device with lead structure within the planar area of the device.
  165. Blonder Greg E. (Summit NJ) Fulton Theodore A. (Warren NJ), Semiconductor integrated circuit chip-to-chip interconnection scheme.
  166. Kishida Satoru (Itami JPX), Semiconductor integrated circuit device.
  167. Saito Tamio (Tokyo JPX) Yosihara Kunio (Kawasaki JPX), Semiconductor integrated circuit device.
  168. Watanabe Masayuki (Yokohama JPX) Sugano Toshio (Kokubunji JPX) Tsukui Seiichiro (Komoro JPX) Ono Takashi (Akita JPX) Wakashima Yoshiaki (Kawasaki JPX), Semiconductor integrated circuit device and method of manufacturing the same.
  169. Fukuta Masumi (Machida JPX) Narita Hisatoshi (Hino JPX), Semiconductor integrated circuit device having a multi-layered wiring board for ultra high speed connection.
  170. Hawkins George W. (Mesa AZ), Semiconductor package having leads that break-away from supports.
  171. Hebert David F. (Hayward CA), Semiconductor package with tape mounted die.
  172. Sugano Toshio (Kokubunji) Nagaoka Kohji (Tobu) Tsukui Seiichiro (Komoro) Wakashima Yoshiaki (Kawasaki) Tanimoto Michio (Kokubunji) Watanabe Masayuki (Yokohama) Sakaguchi Suguru (Chigasaki) Nishi Kuni, Semiconductor stacked device.
  173. Adlerstein, Michael G., Semiconductor structures and manufacturing methods.
  174. Beckham Keith F. (Newburgh NY) Kolman Anne E. (Wappingers Falls NY) McGuire Kathleen M. (Fishkill NY) Puttlitz Karl J. (Wappingers Falls NY) Quinones Horatio (Peekskill NY), Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and pr.
  175. Etzel Stephen J. (Woodstock CT), Solderless connection apparatus.
  176. Lauffer Donald K. (San Diego CA) Sanwo Ikuo J. (San Marcos CA) Rostek Paul M. (San Diego CA), Stackable integrated circuit chip package with improved heat removal.
  177. Kane Milburn H. (Austin TX) Roby John G. (Cedar Park TX) Schrottke Gustav (Austin TX), Stacked DCA memory chips.
  178. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
  179. Salatino Matthew M. (Satellite Beach FL), Stacked configuration for integrated circuit devices.
  180. Mueller Wolfgang R. (Wappingers Falls NY) Spencer ; II Gwynne W. (Poughkeepsie NY), Stacked double density memory module using industry standard memory chips.
  181. Yamamura Keiji (Sakurai JPX) Yoshida Hirokazu (Osaka JPX), Structure for mounting a semiconductor device.
  182. Joshi Kailash C. (Endwell NY) Spaight Ronald N. (Vestal NY), Studded chip attachment process.
  183. Higgins ; III Leo M. (Austin TX) McShane Michael B. (Austin TX), TAB tape translator for use with semiconductor devices.
  184. Loo Mike C. (San Jose CA), Tab semiconductor package with cushioned land grid array outer lead bumps.
  185. Niki Kenichi (Amagasaki JPX) Kokogawa Toru (Amagasaki JPX) Takasago Hayato (Amagasaki JPX), Tape carrier for assembling an IC chip on a substrate.
  186. Haghiri-Tehrani Yahya (Munich DEX), Terminal arrangement for integrated circuit device.
  187. Jamison John W. (Palm Springs CA) Allen Robert E. (Mission Viejo CA), Test connector for electrical devices.
  188. Blonder Greg E. (Summit NJ) Fulton Theodore A. (Warren NJ), Textured metallic compression bonding.
  189. Woodman John K. (601 Mystic La. Foster City CA 94404), Three dimensional integrated circuit package.
  190. Golubic Theodore R. (Phoenix AZ), Three dimensional interconnected integrated circuit.
  191. Cray Seymour R. (Chippewa Falls WI) Krajewski Nicholas J. (Elk Mound WI), Three dimensionally interconnected module assembly.
  192. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
  193. Duffek Edward F. (Cupertino CA) Funk Ernest J. (Cupertino CA) Jankowski Alfred S. (San Jose CA) Lane Jack C. (Saratoga CA) Lehner William L. (Los Altos Hills CA) Oliver Floyd F. (Los Altos CA) Schnei, Two part package for a semiconductor die.
  194. Burns Carmen D. (Austin TX), Ultra high density integrated circuit package.
  195. Burns Carmen D. (Austin TX), Ultra high density integrated circuit packages method and apparatus.
  196. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Ultra high density pad array chip carrier.
  197. Smith Michael C. (Costa Mesa CA) Smith ; Jr. Hal W. (Costa Mesa CA), Ultrasonic wire bonder wire formation and cutter system.
  198. Khandros Igor Y. (Peekskill NY) Distefano Thomas H. (Bronxville NY), Wafer-scale techniques for fabrication of semiconductor chip assemblies.
  199. Shibasaka Mitsusada (Fujisawa JPX) Miyahara Yuichi (Kawasaki JPX), Wire bonding inspection equipment.

이 특허를 인용한 특허 (16)

  1. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  2. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung, Chip package.
  3. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung, Chip package.
  4. Lee, Jin-Yuan; Lin, Eric, Circuit component with conductive layer structure.
  5. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  6. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  7. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  8. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  9. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  10. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  11. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  12. Felton, Mickey S.; Paul, Eddy M.; Frangioso, Ralph C., Mid-plane assembly.
  13. Lin, Mou-Shiung; Peng, Bryan, Multiple chips bonded to packaging structure with low noise and multiple selectable functions.
  14. Lin, Mou-Shiung; Chou, Chiu-Ming, Semiconductor chip and method for fabricating the same.
  15. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  16. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로