초록 ▼

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315) .

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315) . The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor ( 401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor ( 217) describing the received packet's payload.

대표청구항 ▼

What is claimed is: 1. An integrated circuit comprising: a plurality of data stream inputs and/or outputs that receive and/or transmit streams of data; a plurality of data stream processors that process the streams of data, each data stream processor is programmable and being coupled to a data stre

What is claimed is: 1. An integrated circuit comprising: a plurality of data stream inputs and/or outputs that receive and/or transmit streams of data; a plurality of data stream processors that process the streams of data, each data stream processor is programmable and being coupled to a data stream input and/or data stream output and each data stream processor processing a stream of data from the data stream input and/or output, the data stream processor is coupled to as the data stream is received from the data stream input and/or transmitted to the data stream output, each data stream processor including: a writeable instruction memory containing instructions, and a control data processor that controls the data stream processor by sequentially executing instructions from the writeable instruction memory; and the integrated circuit further comprising: an aggregator to perform receive aggregation to certain of the data stream processors that receive a data stream and to perform transmit aggregation to certain of the data stream processors that transmit a data stream, so that the aggregated data stream processors cooperate in processing a stream of data; a context processor that responds to information received from a given data stream processor that is processing a data stream to produce information about the given data stream's context and provide the context information to the given data stream processor; the given data stream processor using the context information to process the data stream; and wherein the integrated circuit being constructed on one chip. 2. The integrated circuit set forth in claim 1 wherein: the control data processor is a general-purpose microprocessor that has an industry-standard architecture, whereby programs for the control data processor are developed using standard tools for the architecture. 3. The integrated circuit set forth in claim 1 wherein: the streams of data include a serial stream and a parallel stream. 4. The integrated circuit set forth in claim 1 wherein the aggregator comprises: configurable interconnections between the aggregated data stream processors; a configurable operation coordinator that coordinates operation of the aggregated data stream processors; and a writeable configurator that specifies the configurable interconnections and the configurable operation coordinator as required to aggregate the data stream processors. 5. The integrated circuit set forth in claim 1 wherein: a data stream input and/or output includes a plurality of I/O pins that receive and/or transmit signals and the integrated circuit further comprises: a writeable configuration specifier for specifying a configuration of a data stream input and/or output; and configuration circuitry coupled between the plurality of I/O pins and the data stream processor and responsive to the configuration specifier for configuring the data stream input and/or output as specified by the configuration specifier, whereby the integrated circuit may be used with a plurality of transmission protocols. 6. The integrated circuit set forth in claim 1 wherein each data stream processor further comprises: a receive processor that operates under control of the control data processor to process the data stream received from the data stream input and/or a transmit processor that operates under control of the control data processor to process the data stream for output to the data stream output. 7. The integrated circuit set forth in claim 6 wherein each of the receive processor or the transmit processor further comprises: a writeable instruction memory containing instructions; and the receive processor or the transmit processor sequentially executes certain of the instructions to process the data stream. 8. The integrated circuit set forth in claim 6 wherein: the receive processor and/or the transmit processor have a plurality of processing components and are configurable to bypass one or more of the components in processing the data streams. 9. The integrated circuit set forth in any one of claims 1 through 8 wherein: a stream of data contains control data and payload; a received stream of data is processed in a receiving data stream processor to extract the control data and the payload and a transmitted stream of data is processed in a transmitting data stream processor to add control data to the payload; and the integrated circuit further comprises a buffer manager coupled to the data stream processors that provides addresses of buffers for storing payload and responds to a write operation with a buffer address to write payload to the addressed buffer and to a read operation with a buffer address to read payload from the addressed buffer; and a queue manager coupled to the data stream processors that manages queues of descriptors of payload, each descriptor including at least a buffer address, the queue manager responding to an enqueue command by enqueuing a descriptor provided with the command to a queue specified in the command and responding to a dequeue command by dequeuing a descriptor from the queue specified in the command, a data stream processor responding to a received stream of data by performing a write operation to the buffer manager with the received data stream's payload and an address provided by the buffer manager and performing an enqueue operation with a descriptor containing the address and transmitting a stream of data by performing a dequeue operation, using the address in a descriptor obtained as a result of the dequeue operation in a read operation to the buffer manager, producing a data stream using the payload received from the buffer manager, and transmitting the produced data stream.