IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0352060
(2003-01-28)
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우선권정보 |
JP-2002-066296(2002-03-12) |
발명자
/ 주소 |
- Yamamoto,Yukio
- Mazawa,Shiro
- Inoue,Takao
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출원인 / 주소 |
- Yamamoto,Yukio
- Mazawa,Shiro
- Inoue,Takao
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대리인 / 주소 |
Mattingly, Stanger, Malur &
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인용정보 |
피인용 횟수 :
2 인용 특허 :
7 |
초록
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An error correction decoding unit performs error correction decoding of an inputted data series. A first memory is written with the data series subjected to error correction decoding by the error correction decoding unit. When the data series undergoing error correction decoding is written to the fi
An error correction decoding unit performs error correction decoding of an inputted data series. A first memory is written with the data series subjected to error correction decoding by the error correction decoding unit. When the data series undergoing error correction decoding is written to the first memory, an address generator supplies write addresses and when the data series written to the first memory is read out of the first memory at random, the address generator supplies random read addresses.
대표청구항
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What is claimed is: 1. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address ge
What is claimed is: 1. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, and wherein said address generator randomly reads the data series written to said first memory by using said random mad addresses when a result of said decision indicates that said random read addresses correspond to data storage portions on said first memory, and it randomly reads the data series written to said first memory by using different random read addresses substituting for said random read addresses when said random read addresses do not correspond to any data storage portion on said first memory. 2. A turbo decoder according to claim 1, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 3. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, wherein said address generator includes: an address conversion section for converting values pursuant to said predetermined rule into said random read addresses, a second memory for storing said random read addresses converted by said address conversion section, and an address control section for controlling write of said converted random read addresses to said second memory or read of said random read addresses from said second memory, whereby when said decision result indicates that a random read address does not correspond to any data storage portion on said first memory, said address control section overwrites said random read address which has already been written to said second memory with a random read address converted immediately subsequently to said random read address. 4. A turbo decoder according to claim 3, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 5. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, and wherein said address control section stops reading a random read address from said second memory during a predetermined period following start of write to said second memory and starts reading a random read address from said second memory after said predetermined period has elapsed, said predetermined period complying with the total of random read addresses not corresponding to any data storage portion on said first memory. 6. A turbo decoder according to claim 5, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 7. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, wherein said address generator includes: a plurality of address conversion sections for converting values pursuant to said predetermined rule into said random read addresses; a correction section for inputting mutually different values pursuant to said predetermined rule to respective ones of said plurality of address conversion sections; an address monitoring section for deciding whether random read addresses converted by the respective ones of said plurality of address conversion sections correspond to data storage portions on said first memory; and an address selection section responsive to a decision result by said address monitoring section to select one of random read addresses converted by the respective ones of said plurality of address conversion sections, whereby the random read address selected by said address selection section is used to randomly read the data series written to said first memory. 8. A turbo decoder according to claim 7, wherein each of said plurality of address conversion sections has priority; said address selection section selects, from random read addresses so determined by said address monitoring section as to correspond to data storage portions on said first memory, a random read address converted by an address conversion section having higher priority; said address monitoring section corrects a value inputted to said correction section in accordance with the priority of said address conversion section which has converted said selected random read address; and said correction section inputs, as values pursuant to said predetermined rule, values resulting from addition of a plurality of mutually different fixed values to said corrected value to the respective ones of said plurality of address conversion sections. 9. A turbo decoder according to claim 8, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 10. A turbo decoder according to claim 7, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 11. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, wherein said address generator includes: an address conversion section for converting values pursuant to said predetermined rule into random read addresses; an address monitoring section for deciding whether said random read addresses converted by said address conversion section correspond to data storage portions on said first memory; and an address control section responsive to a decision result by said address monitor section to control reading of the data series written to said first memory so as to cause it to stop temporarily and processing of a peripheral circuit of said first memory so as to cause it to stop temporarily. 12. A turbo decoder according to claim 11, wherein when said decision result indicates that said random read addresses correspond to data storage portions on said first memory, said address control section uses said random read addresses to control reading of the data series written to said first memory, and when a random read address does not correspond to any data storage portion on said first memory, said address control section stops delivering said random read address and uses a random read address delivered immediately before said random read address to control reading of the data series written to said first memory. 13. A turbo decoder according to claim 12, wherein deciding a random read access address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 14. A turbo decoder according to claim 11, wherein deciding a random read access address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 15. A turbo decoder comprising: an error correction decoding unit for performing error correction decoding of an inputted data series; a first memory to which the data series subjected to error correction coding by said error correction decoding unit is written; and an address generator for supplying, when writing said data series undergoing error correction decoding is written to said first memory, write addresses and when said data series written to said first memory is read out of said first memory, supplying random read addresses, wherein said address generator converts values pursuant to a predetermined rule into said random read addresses and decides whether said random read addresses correspond to data storage portions on said first memory, and wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 16. A radio base station comprising: an antenna; a radio frequency processing unit connected to said antenna; a baseband unit connected to said radio frequency processing unit; and a communication interface for providing interface between said baseband unit and a communication network, wherein: said baseband unit includes a turbo decoder for decoding coded data, said turbo decoder includes: an error correction decoding unit for performing error correction decoding of data series inputted through said radio frequency processing unit, a first memory written with the data series subjected to error correction decoding by said error correction decoding unit, and an address generator for supplying write addresses when said data series undergoing error correction decoding is written to said first memory and supplying random read addresses when the data series written to said first memory is read out of said first memory at random, said address generator being adapted to convert values pursuant to a predetermined rule into said random read addresses and being operative to decide whether said random read addresses correspond to data storage portions on said first memory. 17. A radio base station according to claim 16, wherein said address generator includes: an address conversion section for converting values pursuant to said predetermined rule into said random read addresses; a second memory for storing the random read addresses converted by said address conversion section; and an address control section for controlling writing of said converted random read addresses to said second memory or reading of said random read addresses from said second memory, whereby when the decision result indicates that a random read address does not correspond to any data storage portion on said first memory, said address control section overwrites said random read address which has already been written to said second memory with a random read address converted immediately subsequently to said random read address. 18. A radio base station according to claim 17, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 19. A radio base station according to claim 16, wherein said address generator includes: a plurality of address conversion sections for converting values pursuant to said predetermined rule into said random read addresses; a correction section for inputting mutually different values pursuant to said predetermined rule to respective ones of said plurality of address conversion sections; an address monitoring section for deciding whether random read addresses converted by the respective ones of said plurality of address conversion sections correspond to data storage portions on said first memory; and an address selection section responsive to the decision result by said address monitoring section to select, from the random read addresses converted by the respective ones of said plurality of address conversion sections, one random read address, whereby the random read address selected by said address selection section is used to randomly read the data series written to said first memory. 20. A radio base station according to claim 19, wherein deciding a random mad address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 21. A radio base station according to claim 16, wherein said address generator includes: an address conversion section for converting values pursuant to a predetermined rule into said random read addresses; an address monitoring section for deciding whether said random read addresses converted by said address conversion section correspond to data storage portions on said first memory; and an address control section responsive to the decision result by said address monitoring section to control reading of the data series written to said first memory so as to cause it to stop temporarily and processing of a peripheral circuit of said first memory so as to cause it to stop temporarily. 22. A radio base station according to claim 21, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 23. A radio base station according to claim 16, wherein deciding a random read address as to whether to correspond to a data storage portion on said first memory is made by deciding whether said random read address exceeds a bit number resulting from subtraction of tail bits from an information bit number of said data series subject to error correction decoding. 24. A turbo encoder comprising: a first memory to which transmission data is written; an address generator for supplying write addresses when said transmission data is written to said first memory and supplying random read addresses when said transmission data written to said first memory is randomly read out of said first memory; and a convolutional encoder for performing convolutional coding of said transmission data read out of said first memory at random by means of said address generation unit, said address generator being adapted to convert values pursuant to a predetermined rule into said random read addresses and being operative to decide whether said random read addresses correspond to data storage portions on said first memory. 25. A turbo encoder according to claim 24, wherein said address generator includes: an address conversion section for converting values pursuant to said predetermined rule into said random read addresses; a second memory for storing the random read addresses converted by said address conversion section; and an address control section for controlling write of said converted random read addresses to said second memory or mad of said random read addresses from said second memory, whereby when the decision result indicates that a random read address does not correspond to any data storage portion on said first memory, said address control section overwrites said random read address which has already been written to said second memory with a random read address converted immediately subsequently to said random read address. 26. A turbo encoder according to claim 24, wherein said address generator includes: a plurality of address conversion sections for converting values pursuant to said predetermined rule into said random read addresses; a correction section for inputting mutually different values pursuant to said predetermined rule to respective ones of said plurality of address conversion sections; an address monitoring section for deciding whether random read addresses converted by the respective ones of said plurality of address conversion sections correspond to data storage portions on said first memory; and an address selection section responsive to the decision result by said address monitoring section to select, from the random read addresses converted by the respective ones of said plurality of address conversion sections, one random read address, whereby the random read address selected by said address selection section is used to randomly read transmission data written to said first memory. 27. A turbo encoder according to claim 24, wherein said address generator includes: an address conversion section for converting values pursuant to said predetermined rule into said random read addresses; an address monitoring section for deciding whether said random read addresses converted by said address conversion section correspond to data storage portions on said first memory; and an address control section responsive to the decision result by said address monitoring section to control reading of said transmission data written to said first memory so as to cause it to stop temporarily and processing of a peripheral circuit of said first memory so as to cause it to stop temporarily. 28. A radio base station having a communication interface for providing interface to a communication network, a baseband unit connected to said communication interface, a radio frequency processing unit connected to said baseband unit and an antenna connected to said radio frequency processing unit, wherein said baseband unit comprises a turbo encoder for coding transmission data transmitted through said communication interface, said turbo encoder including: a first memory to which said transmission data is written; an address generator for supplying write addresses when said transmission data is written to said first memory and supplying random read addresses when said transmission data written to said first memory is randomly read out of said first memory; and a convolutional encoder for performing convolutional coding of the transmission data read out of said first memory at random by said address generator, said address generator being adapted to convert values pursuant to said predetermined rule into said random read addresses and being operative to decide whether said random read addresses correspond to data storage portions on said first memory.
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